Selected papers for R. Jacob Baker.

Selected Talks

* Li, K., Saxena, V., and Baker, R.J. (2008) "The Baker ADC: An Overview,", an online seminar in Windows Media format found here.
* Saxena, V. and Baker, R.J., (2007-2008) "High-Speed Op-Amp Design: Compensation and Topologies for Two and Three Stage Designs," presented at various universities and companies. Vishal Saxena Opamps Matlab Design Kit.zip
Baker, R.J., (2006-2008) "Circuit Design for MLC Flash: Towards a Semiconductor Replacement for the Hard Disk Drive," presented at various universities and companies.
Baker, R.J., (2007) Terman Award Acceptance Speech, given at the Frontiers in Education Conference (FIE 2007), Milwaukee, WI, October 11, 2007.
Baker, R.J., (2007) "The One-Transistor, One-Capacitor (1T1C) Dynamic Random Access Memory (DRAM), and its Impact on Society," presented at the Franklin Institute, in the symposium honoring Dr. Robert H. Dennard and his receipt of the 2007 Benjamin Franklin Medal in Electrical Engineering, April 25, 2007.
Baker, R.J. and Saxena, V., (2007) "Design of Bandpass Delta Sigma Modulators: Avoiding Common Mistakes," presented at various universities and companies.
Baker, R.J., (2001-2006) "Sensing Circuits for Resistive Memory," presented at various universities and companies.
Hadrick, M. and Baker, R.J., (2005) "Sensing in CMOS Imagers using Delta-Sigma Modulation," a general presentation of our work in this area.
Baker, R.J. (2005) "Design of High-Speed CMOS Op-Amps for Signal Processing," IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), April, 2005
Baker, R.J. (2004) "Delta-Sigma Modulation for Sensing," IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), April, 2004
Rivera, B. and Baker, R.J. (2001) "Design and Layout of Schottky Diodes in a Standard CMOS Process," MURI Review, November, 2001.

* Favorite of CMOSedu.com users!!!

Publications

2009

Baker, R.J., “CMOS Mixed-Signal Circuit Design, Second Edition,” Wiley-IEEE, 2009. ISBN 978-0-470-29026-2
Regner, J., Balasubramanian, M., Cook, B., Li, Y., Kassayebetre, H., Sharma, A., Baker, R.J., Campbell, K.A., “Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip,” Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 28-31, April, 2009.
Gupta, S. Saxena, V., Campbell, K.A., and Baker, R.J., “W-2W Current Steering DAC for Programming Phase Change Memory,” Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 59-62, April, 2009.
Rapole, H., Rajagiri, A., M. Balasubramanian, Campbell, K.A., and Baker, R.J., “Resistive Memory Sensing Using Delta-Sigma Modulation,” Proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 63-66, April, 2009.
Kassayebetre, H., Regner, J., Rajagiri, A., Sharma, A., Hay, R.R., Baker, R.J., and Campbell, K.A., “Surface Acoustic Wave Device Fabrication using Zinc Oxide and Chalcogenide Thin Films,” poster presentation at the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), April, 2009.

2008

Baker, R.J., “CMOS Circuit Design, Layout, and Simulation, Revised Second Edition,” Wiley-IEEE, 2008. ISBN 978-0-470-22941-5
Ande, H.K., Busa, P., Balasubramanian, M., Campbell, K.A., and Baker, R.J., "A New Approach to the Design, Fabrication, and Testing of Chalcogenide-Based Multi-State Phase-Change Nonvolatile Memory,", proceedings of the 51st Midwest Symposium on Circuits and Systems, pp. 570-573, August 10-13, 2008.

Saxena, V., and Baker, R.J., "Compensation of CMOS Op-Amps using Split-Length Transistors,", proceedings of the 51st Midwest Symposium on Circuits and Systems, pp. 109-112, August 10-13, 2008.
Estrada, D., Ogas, M.L., Southwick III, R.G., Price, P.M., Baker, R.J., and Knowlton, W.B., “Impact of Single pMOSFET Dielectric Degradation on NAND Circuit Performance,” Microelectronics Reliability, 48(3) (2008) pp. 354–363.
Saxena, V., and Baker, R.J., "Indirect Compensation Technique for Low-Voltage Op-Amps,", proceedings of the 3rd Annual Austin Conference on Integrated Systems and Circuits (ACISC), May 7-9, 2008.
Cahoon, C., and Baker, R.J., "Low-Voltage CMOS Temperature Sensor Design using Schottky Diode-Based References," proceedings of the IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 16-19, April, 2008.

2007

Keeth, B., Baker, R.J., Johnson, B., and Lin, F., “DRAM Circuit Design: Fundamental and High-Speed Topics,” Wiley-IEEE, 2007. ISBN 978-0-470-18475-2
Baker, R.J., “CMOS Circuit Design, Layout, and Simulation, Revised Second Edition” Wiley-IEEE, 2007. ISBN 978-0-470-22941-5
Knowlton, W.B., Araujo, D., Price, P.M., Brotherton, J., Coonse, K., Hendricks, K., Southwick III, R.G., Henderson, J., Oxford, J., Moll, A., Kuang, W., and Baker, R.J., “Progress Towards a Biomolecular Nanowire Sensor Array for Biomedical Applications,” invited talk presented at the 6th Annual INBRE/COBRE Research Conference, Moscow, ID, August 6, 2007
Knowlton, W.B., Araujo, D., Price, P.M., Brotherton, J., Coonse, K., Southwick III, R.G., Oxford, J., Moll, A., Baker, R.J., and Kuang, W., “Development of Biomolecular Nanostructure Sensor Arrays,” presented at the Sensors and Sensor Technology session for the program of the 88th annual meeting of the AAAS, Pacific Division, June 2007, Boise, ID
Knowlton, W.B., Kuang, W., Araujo D., Price, P.M., Brotherton, J., Coonse, K. Bollschweiler, L., Southwick, R., Oxford, J. Moll, A., and Baker, R.J., “Nanofabrication of 3D Sensor Arrays for Detection,” Advanced Fuel Cycle Workshop, May 8-9, 2007, Boise, ID

2006

Leslie, M.B., and Baker, R.J., "Noise-Shaping Sense Amplifier for MRAM Cross-Point Arrays," IEEE Journal of Solid State Circuits, Vol. 41, No. 3, pp. 699-704.
Loo, S.M., Cole, J., Youngberg, R., Baker, R.J., Gribb, M.M., “Field-programmable gate array in a miniature ion mobility spectrometer sensor system,” Proceedings of the 2006 International Conference on Embedded Systems & Applications, June 26-29, 2006, Las Vegas, NV.
Saxena, V., and Baker, R. J., "Indirect Feedback Compensation of CMOS Op-Amps,", IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 3-4, April, 2006.
Duvvada, K., Saxena, V., and Baker, R. J., "High Speed Digital Input Buffer Circuits,", IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 11-12, April, 2006.
Saxena, V., Plum, T.J., Jessing, J.R., and Baker, R. J., "Design and Fabrication of a MEMS Capacitive Chemical Sensor System,", IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 17-18, April, 2006.
Gorseth, T.L., Estrada, D., Kiepert, J., Ogas, M.L., Cheek, B.J., Price, P.M., Baker, R.J., Bersuker, G., and Knowlton, W.B., “Preliminary study of NOR digital response to single pMOSFET dielectric degradation,” IEEE/EDS Workshop on Microelectronics and Electron Devices (WMED), pp. 31-32, April, 2006.

Sevier, D., Gribb, M., Plumlee, D., Moll, A.J., Hill, H.H., Hong, F., Baker. R.J., Loo, S.M., Walters, R., and Imonigie, J., “An In-Situ Ion Mobility Spectrometer Sensor System for Detecting Gaseous VOCs in the Vadose Zone,” Fourth International Conference on Unsaturated Soils (UNSAT ‘06) Conference, April 2-6, 2006, Carefree, AZ.

2005

Gribb, M., Hill, H.H., Baker, R.J., Loo, S.M., and Moll, A.J., “Ion Mobility Spectrometer (IMS) Sensor Project,” presented at the Environmental & Subsurface Science Symposium, Inland Research Alliance, Sept. 19-21, 2005, Big Sky, Montana.

Ogas, M.L., Price, P.M., Kiepert J., Baker R.J., Bersuker G., and Knowlton W.B., “Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics,” 2005 IEEE Integrated Reliability Workshop, October 2005.
Butler, D.L, and R.J. Baker, "Low-Voltage Bandgap Reference Design Utilizing Schottky Diodes,", proceedings of the 2005 Midwest Symposium on Circuits and Systems.

2004

Baker, R.J., “CMOS Circuit Design, Layout, and Simulation, Second Edition” Wiley-IEEE, 2004. ISBN 978-0471700555
Ogas, M. L., Southwick III, R.G., Cheek, B.J., Baker, R.J., Bersuker, G., and Knowlton, W.B., “Survey of Oxide Degradation in Inverter Circuits Using 2.0nm MOS Devices,” in proceedings of the 2004 IEEE International Integrated Reliability Workshop, Oct. 2004, pp. 32-36.

Cheek, B.J., Southwick III, R.G., Ogas, M.L., Nagler, P.E., Whelchel, D., Kumar, S., Baker, R. J., and Knowlton, W. B., “Preliminary Soft Breakdown (SBD) Effects In CMOS Building Block Circuits,” poster presentation at 2004 IEEE International Integrated Reliability Workshop, Oct. 18-21.
Ogas, M., Southwick III, R. Cheek, B., Lawrence, C., Kumar, S., Haggag, A., Baker, R.J., and Knowlton, W.B., “Multiple Waveform Pulse Voltage Stress Technique for Modeling Noise in Ultra Thin Oxides,” poster presentation at Workshop on Microelectronics and Electron Devices, Boise, Idaho, April 16, 2004.
Cheek, B. J., Stutzke, N., Santosh K., Baker, R.J., Moll, A.J., and Knowlton, W.B., "Investigation of Circuit-Level Oxide Degradation and its Effect on CMOS Inverter Operation Performance and MOSFET Characteristics,", 2004 IEEE International Reliability Physics Symposium, April, 25-29.

2003

Stutzke, N., Cheek, B.J., Wiscombe, M., Lowman, T., Kumar, S. Baker, R.J., Moll, A.J. and Knowlton, W.B., "Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics,", 2003 IEEE International Integrated Reliability Workshop, Oct, 20-23.
Ogas M. L., Southwick, R.G., Cheek, B.J., Lawrence, C.E., Kumar, S., Haggag, A., Baker, R.J., and Knowlton, W.B., “Investigation of Multiple Waveform Pulse Voltage Stress (MWPVS) Technique in Ultra-Thin Oxides, poster presentation at the 2003 IEEE International Integrated Reliability Workshop Oct, 20-23.
Baker, R.J., "Mixed-Signal Design in the Microelectronics Curriculum,” IEEE University/Government/Industry Microelectronics (UGIM) Symposium, June 30 - July 2, 2003.
Hartman, J.A., Baker, R.J., Gribb, M., Hill, H.H., Jessing, J., Moll, A.J., Prouty, W., and Russell, D., “A Miniaturized Ion Mobility Spectrometer (IMS) Sensor for Wireless Operation,” FAME (Frontiers in Assessment Methods for the Environment) Symposium, Sponsored by NSF, Minneapolis, Minnesota, August 10-13, 2003.
Lawrence, C.E., Cheek, B.J., Lawrence, T.E., Kumar, S., Haggag, A., Baker, R.J., and Knowlton, W.B., "Gate Dielectric Degradation Effects on nMOS Devices Using a Noise Model Approach,", IEEE University/Government/Industry Microelectronics (UGIM) Symposium, June 30 - July 2.

2002

Cheek, B.J., Lawrence, C.E., Lawrence, T.E., Gomez, J., Caldwell, T., Kiri, D., Kumar, S., Baker, R.J., Moll, A.J., and Knowlton, W.B., "Gate Dielectric Degradation Effects on nMOS Devices and Simple IC Building Blocks (SICBBs)," IEEE Electron Devices Society Boise Meeting, Boise, ID Oct. 25.
Lawrence, C.E., Cheek, B.J., Caldwell, T.E., Lawrence, T., Kiri, D., Kumar, S., Baker, R.J., Moll, A.J., and Knowlton, W.B., “Pulse voltage stressing of ultrathin gate oxides in NMOS devices,” poster session at IEEE International Integrated Reliability Workshop, October 21-24.
Cheek, B.J., Lawrence, C.E., Lawrence, T.E., Caldwell, T., Kiri, D., Kumar, S., Baker, R.J., Moll, A.J., and Knowlton, W.B., “Circuit level reliability of ultrathin gate oxides for SICBBs: Preliminary study concentrated on the effect of stress on the NMOSFET of an inverter,” poster session at IEEE International Integrated Reliability Workshop, October 21-24.
Baker, R.J., "Sensing Circuits for Resistive Memory," IEEE Electron Devices Society Boise Meeting, Boise, ID Oct. 25.

2001

Rivera B., Baker R. J., Melngailis J., "Design and Layout of Schottky Diodes in a Standard CMOS Process," 2001 International Semiconductor Device Research Symposium, Washington DC, Dec. 2001.

2000

Keeth, B. and Baker, R.J., “DRAM Circuit Design: A Tutorial,” IEEE Press, 2000. ISBN 978-0-780-36014-3
Hess, H.L., and Baker, R.J., "Transformerless Capacitive Coupling of Gate Signals for Series Operation of Power MOS Devices," IEEE Transactions on Power Electronics, Vol. 15, No. 5, pp. 923-930.
Hess, H.L., and Baker, R.J., “Easier Method to Simultaneously Trigger Series-Connected MOS Devices,” Power Systems World Conference 2000, Boston, Massachusetts, September 2000.

1999

Lin, F., Miller J., Schoenfeld A., Ma, M. and Baker, R.J., "A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM," IEEE Journal of Solid State Circuits, Vol. 34, No. 4, pp. 565-568.
Hess, H.L., and Baker, R.J., “Transformerless Capacitive Coupling of Gate Signals for Series Operation of Power MOSFET Devices,” International Electric Machines and Drives Conference, Seattle, Washington, May 1999, pp. 673-676.
Baker, R.J., "A windows based integrated circuit design tool for distance education," International Conference on Simulation and Multimedia in Engineering Education.

1998

Chen H. and Baker R.J., "A CMOS Standard-Cell Library for the PC-based LASI Layout System," 41st Midwest Symposium on Circuits and Systems," August 9-12, 1998
Liu, S., and Baker, R.J., "Process and temperature performance of a CMOS beta-multiplier voltage reference,” 41st Midwest Symposium on Circuits and Systems," August 9-12, 1998.

1997

Baker, R.J., Li, H.W., and Boyce, D.E., “CMOS Circuit Design, Layout, and Simulation,” IEEE Press. ISBN 978-0-780-33416-8.
Boyce D.E. and Baker R.J., "A Complete Layout System for the PC," 40th Midwest Symposium on Circuits and Systems, August 3-6, 1997.

1996

Bruce, J.D., Li H.W., Dallabetta, M.J., and Baker, R.J., "Analog layout using ALAS!" IEEE Journal of Solid State Circuits, Vol. 31, No. 2, pp. 271-274.

1995

Li H.W., Dallabetta M.J., and Baker R.J., "An interactive impulse response extraction system," Review of Scientific Instruments 66(10), 5092-5095.
Ward, S.T., Baker, R.J. and Li. H.W., "A microchannel plate image intensifier gating circuit capable of pulse widths from 30 ns to 10 us," Measurement Science and Technology, Vol. 6, No. 11, pp. 1631-1633.
Keeth, B., R. J. Baker, and H. W. Li., "CMOS transconductor VCO with adjustable operating and center freqencies," Electronics Letters 31(17), 1397-98.

1994

Baker, R. J., "Time domain operation of the TRAPATT diode for picosecond-kilovolt pulse generation," Review of Scientific Instruments 65(10), 3286-88.
Baker, R. J. and S. T. Ward, "Designing nanosecond high voltage pulse generators using power MOSFETs," Electronics Letters 30(20), 1634-35.
Baker, R. J. and B. P. Johnson, "Sweep circuit design for a picosecond streak camera," Measurement Science and Technology 5(4).

1993

Baker R. J., D. J. Hodder, B. P. Johnson, P. C. Subedi, and D. C. Williams, "Generation of kilovolt-subnanosecond pulses using a nonlinear transmission line" Measurement Science and Technology 4(8), 893-95.
Baker R. J. and Johnson B. P., "Series operation of power MOSFETs for high speed, high voltage switching applications," Review of Scientific Instruments 65(6).
Baker R. J. and Johnson B. P., "Applying the Marx bank circuit configuration to power MOSFETs," Electronics Letters 29(1), 56-57.

1992

Baker R. J. and Johnson B. P., "Stacking power MOSFETs for use in high speed instrumentation," Review of Scientific Instruments 63(12), 5799-5801.
Baker R. J. and Johnson B. P., "A 500 Volt nanosecond pulse generator using cascode connected power MOSFETs," Measurement Science and Technology 3 (8), 775-77.

1991

Baker, R.J., and Blair, J.J., "Step response considerations and the design of a suitable step generator for high speed digitizer testing," LLNL's Third Annual Workshop on High Speed Digitizers, April 3-4, Las Vegas, Nevada.
Baker R. J., Perryman G. T., and Watts P. W., "A fiber-optically triggered avalanche transistor," IEEE Transactions on Instrumentation and Measurement 40(3), 649-52.
Baker R.J., "High voltage pulse generation using current mode second breakdown in a bipolar junction transistor," Review of Scientific Instruments 62(4), 1031-1036.

1990

Baker R.J. and Pocha, M.D., "Nanosecond switching using power MOSFETs," Review of Scientific Instruments 61(8), 2211-2213.
Baker, R.J., "Step-recovery diodes sharpen pulses," Engineering Design News (EDN) Magazine, pp. 154-156, May 10.

Additional Publications

Baker, R.J., (1993) “Applying Power MOSFETs to the Design of Electronic and Electro-Optic Instrumentation,” Doctoral Dissertation, University of Nevada, Reno.
Baker, R.J., (1988) “A Three Dimensional Numerical Simulation of Short Channel MOSFETs with the Effects of Gate Oxide Charge,” Master’s Thesis, University of Nevada, Las Vegas.
Baker, R.J., (1985) “The Design of a Medium Range Digital Communications Bus,” Senior Design Project, University of Nevada, Las Vegas.

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