EE 5/418 Memory Circuit
Design
Fall 2004, Boise State University
Lecture notes are here.
Instructor: Prof. R. J.
Baker
Course facilitator at Virgina Tech: Prof. R. Hendricks
Textbook: "CMOS
Circuit Design, Layout and Simulation, (Second Edition)" (chapters 16
to 19)
Time: 6:00 – 7:15 pm (
Location: SMITC room 116 (the Simplot Micron Instructional Technology building)
Final exam time:
Tuesday, December 14 6:00 – 8:00 pm (will be different for VT)
Course Description - Design of memory circuits with an emphasis on DRAM. The course will provide detailed and practical information on the transistor level design of memory circuits. Other memory technologies including Flash, MRAM, Glass-based, and SRAM will be discussed. Prerequisite: EE 410 IC Physical Design.
Project – due Tuesday December 7 at the beginning of class. Project information is found here.
Midterm exam – Two parts: take-home and in-class. The in-class portion will be Thursday, October 7, closed book. The take-home portion is due on this Thursday as well. Each part will count for 50% of the overall midterm exam.
Homework:
HW5 – Due Thursday, Oct. 21 – HW5_5418.pdf
HW4 – Due Thursday, Sept. 30 – HW4_5418.pdf
HW3 – Due Tuesday, Sept. 21 – HW3_5418.pdf
HW2 – Due Thursday, Sept. 16 – HW2_5418.pdf
HW1 – Due Tuesday, Sept. 7 – HW1_5418.pdf
Quizzes:
Quiz 6 (counts as two; it will be twice as long) – Tuesday, Nov. 16, covering end of Ch. 17 and Ch. 19 problems 1-20 (open book, closed notes and photocopies)
Quiz 5 – Thursday, Oct. 21, covering HW5 and Ch. 17 problems 1-8
Quiz 4 – Thursday, Sept. 30,
covering HW4 and Ch. 16 problems 14-20
Quiz 3 – Tuesday, Sept. 21, covering HW3
Quiz 2 – Thursday, Sept. 16, covering HW2 and Ch. 16 problems 7-13
Quiz 1 – Tuesday, Sept. 7, covering HW1 and Ch. 16 problems 1-6
Grading (Note for graduate
credit, EE518, you will have an extra exam problem and a more complex project.)
20% Homework
20% Quizzes
20% Midterm
20% Project
20% Final