EE 5/411 CMOS Analog IC Design
Fall 2006, Boise State University

The Fall 2005 course webpage is located here.

The cmosedu.com Google group’s (http://groups.google.com/group/cmosedu) and the email address is cmosedu@googlegroups.com

Lectures notes are available here

Homework assignments are found here

Current grades are here

Instructor: Prof. R. J. Baker

Course TA: Vishal Saxena (send homework to this email address).

Time: 6:00 – 7:15 pm MW (note the time change) Classes begin Monday August 21 and end Friday December 8

Textbook: "CMOS Circuit Design, Layout and Simulation, (Second Edition)" (Chapters 9, 20-24)
Room: Simplot/Micron instructional Technology Center (SMITC) room 116

Availability for off-campus students: see the notes here

Test proctoring for out-of-area students: someone approved by the instructor (professor, teacher, training person at a company, etc.)

Micron and other Boise area students taking the course through extended studies: you will be required to take all exams at Boise State.
Holidays: Labor day (Monday Sept. 4), Thanksgiving break (MWF Nov. 20, 22, 24)
Final exam time: Monday Dec. 11 from 6 to 8 pm

Topics: MOSFET models for analog circuit design, current sources, layout, matching, amplifiers, references, biasing, amplifier and op-amp design. 

Prerequisite: EE 5/410 IC Physical Design 

Policies: Homework is due at the beginning of the lecture; no late homework accepted. Course final exam and project are not returned at the end of the semester.

For Graduate credit (EE 511): a more complex project will be assigned and (sometimes) an additional exam problem will given.

Grading
20% Homework
20% Test1
20% Test2
20% Project 
20% Final

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