EE 5/411 CMOS Analog IC
Design
Fall 2005, Boise State University
Lectures notes are here.
Homework assignments are found here
Current grades are here
Textbook: "CMOS Circuit Design, Layout and Simulation, (Second Edition)" (Chapters 9, 20-24)
Instructor: Prof. R. J. Baker
Course TA:
Time:
Room: Simplot/Micron instructional Technology Center (SMTC) room 118, also
broadcast on K-Net for Micron
employees and others, see distance
education
Holidays: Labor day (Monday Sept. 5), Thanksgiving
break (MWF Nov. 21, 23, 25)
Final exam time: Wednesday Dec. 14 from
Topics: MOSFET models for analog circuit design, current sources, layout, matching, amplifiers, references, biasing, amplifier and op-amp design.
Prerequisite: EE 5/410 IC Physical Design
Policies: Homework is due at the beginning of the lecture; no late homework accepted. Course final exam and project are not returned at the end of the semester.
Micron students: you can view the lectures (live) at Micron;
however, you will be required to take all exams at
Projects: Due Monday December 5. You’ve just been employed by a start-up company, Systems On a Chip R Us (SOCRU). SOCRU was started to integrate the electronics for an entire cell phone on a single chip. You are tasked with the design of a small, high-quality, very low power, audio amplifier for driving a set of high-impedance head phones. Since the cell phone will be used as a music player (where streaming audio will be used to avoid the need for large amounts of memory on the cell phone chip) the performance of your design is critical for quality sounding music reproduction. Some of the specific requirements of the design are:
Process: TSMC’s 180 nm CMOS process
VDD: a 1.5 V battery
Typical load: 600 ohms (is this actually a DC load or an AC load?) in parallel with 100 pF
Closed loop gain of either + 1 or -1 (the amplifier only provides a power gain to drive the load)
Amplifier input resistance: >10k
Frequency response (closed loop): DC to >20kHz
Temperature range: -20C to 70C
Layout area: as small as possible (comment on electromigration concerns with the wiring supplying power to the amplifier’s output stage)
Enable: The amplifier has an enable input that, when high, shuts the audio amplifier off so that the amplifier doesn’t draw current from VDD
Power: the lowest power possible while keeping good THD and output swing (you need to decide what is “good”)
Power Supply Rejection Ratio: Since this design will be integrated with the entire SOC power supply and ground noise immunity are extremely important (so characterize how VDD and ground noise affect the output of the amplifier)
Your design report should discuss: Biasing (and the amplifier(s) configuration you chose and why), temperature behavior, output swing concerns and THD, VDD/ground noise, layout size, PCE, gain-bandwidth product, and a discussion of how a gain of 1 amplifier’s THD is better or worse (and why) than a gain of -1 (with a 20k resistors). Your final report, complete with schematics, simulations (presented in terse yet clear detail), and discussions should be clear so that your bosses, aspiring future multi-millionaires with very busy schedules, can quickly review and determine why you made the choices you did and see that you’ve covered all of the major concerns with the design (you really need to focus a lot of effort on power, THD, and VDD/ground noise since these always seem to be problems in practical design). Also, take a look at how the THD goes up if someone uses a splitter (two sets of head phones are using the audio output jack) on the output of the amplifier so that load drops to 300 ohms in parallel with 200 pF.
The success of SOCRU is riding, in part, on your design skills. Good luck!
Grading
20% Homework
20% Test1
20% Test2
20% Project
20% Final