EE 5/410 Integrated Circuit Physical Design
Spring 2007, Boise State University

 

The Spring 2006 course webpage is located here

 

The cmosedu.com Google group’s (http://groups.google.com/group/cmosedu) and the email address is cmosedu@googlegroups.com

 

Lecture notes are available here

Homework assignments, project information, and due dates are located here

Current grades are here

 

·         For the fabrication of chips in this class, AMI’s 500 nm (C5 with two polysilicon layers and 3 levels of metal) will be used with a MOSIS technology code of SCN3ME_SUBM with a lambda of 300 nm.

·         MOSIS information for this process is located here and the SPICE models are C5_models.txt

·         In this course we will make extensive use of LTspice for SPICE simulation and Electric for Layout.

·         Layout examples using Electric from the lectures are found in ee5410.jelib.

 

Textbook: "CMOS Circuit Design, Layout and Simulation, Second Edition" (Chapters 1-6, 10-15, 18)
Instructor: Prof. R. Jacob Baker Ph.D. P.E. homepage
Time: Mondays and Wednesdays from 5:00-6:15 pm

Course dates: Wednesday, January 17 to Wednesday, May 2

Location: Simplot/Micron instructional Technology Center (SMITC) room 116

Availability for off-campus students: see the notes here

Test proctoring for out-of-area students: someone approved by the instructor (professor, teacher, training person at a company, etc.)

Micron and other Boise area students taking the course through extended studies: you will be required to take all exams at Boise State.

Holidays: February 19 (Presidents day), March 26 and 28 (Spring break)
Final Exam time: Monday May 7 from 5 to 7 pm

Course content – An introduction to CMOS IC design, layout, and simulation. 

MOSFET operation and parasitics. Digital design fundametals, design of digital

logic blocks. PREREQ: EE 322. COREQ EE 323.

For Graduate credit (EE 510): a more complex project will be assigned and (sometimes) an additional exam problem will given.

 

Grading
20% Midterm1
20% Midterm2
20% Homework
20% Project
20% Final

 

Policies

No late work accepted. All assigned work is due at the beginning of class (received email by the time class starts for off-campus students).

Neither the final exam nor final project will be returned at the end of the semester.

Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)

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