EE 5/410 Integrated
Circuit Physical Design
Spring 2006, Boise State University
The cmosedu.com Google group’s (http://groups.google.com/group/cmosedu) and the email address is cmosedu@googlegroups.com
Lecture notes are here
LASI layout directory for the course is here
Homework assignments and due dates are located here
Current grades are here
For the fabrication of chips in this class, AMI’s 500 nm (C5 with two polysilicon
layers and 3 levels of metal) will be used with a MOSIS technology code of SCN3ME_SUBM
(the SUBM scalable design rules used in Lasidrc) and a lambda of 300 nm.
MOSIS information on this process is here.
The SPICE models for this process are models.txt
The course TAs are Priya Sridhar and Sue-Fern Ng (send homework to this email address).
Textbook: "CMOS Circuit Design, Layout and
Simulation, Second Edition" (Chapters 1-6, 10-15)
Instructor: Prof. R. Jacob Baker Ph.D. P.E. homepage
Time:
Course dates: Wednesday, January 18 to Friday, May 5
Location: Simplot/Micron instructional Technology Center (SMTC) room 210
Availability for off-campus students: see the notes here
Test proctoring for off-campus students: someone approved by the instructor (professor, teacher, training person at a company, etc.)
Holidays: February 20
(president’s day), Saturday, March 25 to Sunday, April 2 (spring break from
instruction)
Final Exam time: Monday May 8 from 1 to 3 pm
Course content – An introduction to CMOS IC design, layout, and simulation.
MOSFET operation and parasitics. Digital design fundametals, design of digital
logic blocks. PREREQ: EE 322. COREQ EE 323.
Grading
20% Midterm1
20% Midterm2
20% Homework
20% Project (more advanced project for graduate credit, EE 510)
20% Final (an additional problem for graduate credit, EE 510)
Policies
No late homework accepted. Homework is due at the beginning of class (received email by the time class starts for off-campus students).
Neither the final exam nor final project will be returned at the end of the semester.