Lecture notes and videos for EE 421 Digital Electronics and ECG 621 Digital Integrated Circuit Design, Fall 2015

December 7 – final exam (comprehensive), 6 to 8 PM, open book and closed notes. (A practice exam is found here.)
December 2 – lec27_ee421_ecg621.pdf and lec27_ee421_ecg621_video – review for the final  
November 30 – lec26_ee421_ecg621.pdf and lec26_ee421_ecg621_video – introduction to memory circuits
November 25 – lec25_ee421_ecg621.pdf and lec25_ee421_ecg621_video – dynamic circuits
November 23 – lec24_ee421_ecg621.pdf and lec24_ee421_ecg621_video – clocked CMOS circuits, operation of the DFF
November 18 – lec23_ee421_ecg621.pdf and lec23_ee421_ecg621_video – complex CMOS logic, delay calculations
November 16 – lec22_ee421_ecg621.pdf and lec22_ee421_ecg621_video – even more project discussion
November 11 – Veteran's Day Recess  
November 9 – lec21_ee421_ecg621.pdf and lec21_ee421_ecg621_video – more project discussion, static logic gates
November 4 – lec20_ee421_ecg621.pdf and lec20_ee421_ecg621_video – inverter delay calculations, other inverter configurations
November 2 – lec19_ee421_ecg621.pdf and lec19_ee421_ecg621_video – ring oscillators and buffers
October 28 – lec18_ee421_ecg621.pdf and lec18_ee421_ecg621_video – discuss project
October 26 – lec17_ee421_ecg621.pdf and lec17_ee421_ecg621_video – continue discussing the inverter
October 21 – lec16_ee421_ecg621.pdf and lec16_ee421_ecg621_video – delay through pass gates, start the inverter
October 19 – lec15_ee421_ecg621.pdf and lec15_ee421_ecg621_video – work home work examples, using the digital model, pass gates and transmission gates
October 14 – lec14_ee421_ecg621.pdf and lec14_ee421_ecg621_video – models for digital design
October 12 – midterm exam (open book, closed notes)
October 7 – lec13_ee421_ecg621.pdf and lec13_ee421_ecg621_video – finish Ch. 6, review for midterm exam  
October 5 – lec12_ee421_ecg621.pdf and lec12_ee421_ecg621_video – more IV curves, subthreshold, short–channel MOSFETs
September 30 – lec11_ee421_ecg621.pdf and lec11_ee421_ecg621_video – more threshold voltage discussion, begin IV characteristics of MOSFETs
September 28 – lec10_ee421_ecg621.pdf and lec10_ee421_ecg621_video – start MOSFET operation, strong inversion, depletion, accumulation, threshold voltage
September 23 – lec9_ee421_ecg621.pdf and lec9_ee421_ecg621_video – more resistor layout, laying out wide and long MOSFETs, MOSFET capacitances
September 21 – lec8_ee421_ecg621.pdf and lec8_ee421_ecg621_video – more MOSFET layouts, substrate/well contacts, standard cell frames, hi–res poly layer in the C5 process, poly–poly caps
September 16 – lec7_ee421_ecg621.pdf and lec7_ee421_ecg621_video – the active and poly layers, layout of a MOSFET 
September 14 – lec6_ee421_ecg621.pdf and lec6_ee421_ecg621_video – delay through the metal layers, crosstalk and ground bounce
September 9 – lec5_ee421_ecg621.pdf and lec5_ee421_ecg621_video – the metal layers, laying out a bond pad, capacitance, vias
September 7 – Labor Day Recess  

September 2 – lec4_ee421_ecg621.pdf and lec4_ee421_ecg621_video – diffusion (storage) capacitance, RC delay through an n–well

August 31 – lec3_ee421_ecg621.pdf and lec3_ee421_ecg621_video (no audio) – patterning the n–well, depletion capacitance, Cadence example

August 26 – lec2_ee421_ecg621.pdf and lec2_ee421_ecg621_video – making a design directory in Cadence for the C5 process, start Ch. 2, The Well

August 24 – lec1_ee421_ecg621.pdf and lec1_ee421_ecg621_video – course introduction, setting up Cadence

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