University of Nevada Las Vegas. Department of Electrical and Computer Engineering

The 8-Bit, 32 Word Register File

Design, Analysis and Implementation in the ONSEMI C5 Process

By Brian Wolak

Introduction / Theory of Operation

Register Files (RF) are integrated semiconductor memory circuits most commonly used in RISC architecture to store and access data. While register files are generally much smaller in size with more port access allowing simultaneous high speed read and write functionality, they share many common characteristics with Static Random Access Memory (SRAM) and differ greatly from Dynamic Access Memory (DRAM) due to the unrequired refresh to retain data. Both RF and SRAM protocols use one memory cell to retain a single bit of data combined together to form multiple bit "words" of data. These words are then combined to form a large bank of data storage made up of many words that can be accessed using a unique input address for each word of stored data. Register file size can be denoted using the equation below where m is the number of register addressing bits and n is the number of bits per register. 

Description of Components

Each 8 bit memory cell of my design will follow closely with a traditional SRAM memory architecture 6 transistor topology. The design will also involve a 5-bit address input to allow access to each of the 32 8-bit word registers. This input address will be accessed through the use of a 5:32 row decoder designed using 32 individual 5-bit input NAND gates. The read/write portion of my design will involve a sense amplifier designed to read each bit line and sense voltage difference on a read cycle which is separated from the write portion of the circuit. Because this design does not involve any clocked circuitry it remains advantageous in it's simplicity and extremely low power consumption. 

The Single Bit Memory Cell

Beginning with a single bit of memory storage a 6 transistor (6T) individual memory cell was designed to retain one bit of data. In this topology, as long as the circuit remains powered, data is saved. No refresh is needed as the the circuit shown below shows input/output bit line access using D and Di pins. The WL or word line input is used to turn the cell on or off allowing stored data to reach or be stored through the bit lines during read and write cycles.

6 Transitor Single Memory Cell Circuit

While SRAM memory is inherently designed to be compact and efficient with the purpose of saving costly chip space, I spent a lot of time assuring my design would be as tight as possible to yield a extremely compact overall layout design. Keeping the internal transistors at a minimum size, I chose larger sizes to drive the bit lines allowing them to overpower the internal transistors when performing a write operation. Below is the layout of a single 6 transistor memory cell used in my register file design.

6 Transistor Memory Cell Layout

The 8-Bit Memory "Word"

8-Bit Memory Word Cell Circuit

Combining the single bit cell designed above we use 8 individual memory cells to form an 8-bit word. This will be used 32 times in the register file design and will take the largest portion of layout space. The word lines of each single bit cell will be combined to allow access to all 8 memory cells with one input single, while each cell's bit lines will remain individual allowing individual memory to be stored uniquely in each cell. Shown below is the 8-bit word layout used in my register file design. Standard cell formatting was used to allow the design to remain expandable while maximizing the layout space.

 8-bit Memory Cell Layout

5:32 Row Decoder

Row Decoder Schematic 

In order to access each individual 8-bit word we must include an input decoding device. Designing this device, I began by creating a 5 input NAND gate in CMOS topology which I will use 32 times to provide individual access to each 8-bit word. Combining those individual gates with a 5 input truth table, each word in the 32 word register file will obtain a unique address from the 5-bit input. Below you can see the NAND gate schematic and layout.

5 Input NAND Gate Circuit

5 Input NAND Gate Layout

Combining 32 NAND gates together along with an inverter to each word line, will form the overall decoder device. Below we can see the 5:32 decoder overall schematic using the NAND gate symbol created in Cadence and the associated row decoder truth table.

5:32 Row Decoder and Associated Truth Table

5:32 Row Decoder Layout

Running a simulation to verify operation of the row decoder we achieve the output shown below. We can see that when comparing the truth table to each A[0:4] selection input the proper word line output goes high accordingly meaning each 8-bit word line would turn on the driver transistors making the 8-bit cell active for a read or write sequence.

5:32 Row Decoder Simulation Results

Single Bit Differential Amplifier

When attempting the project as directed I ran into some trouble with flipping individual cells on read and write cycles so I attempted to design a differential amplifier on each bitline pair to account for this. The PMOS devices in this differential or sense amplifier will form a current mirror while the NMOS devices provide an input from B and Bn from each bitline pair and cause the output to swing giving us a true logic value upon read. That output will be ran through a pair of inverters to clean up the signal. Using a topology researched online as well as the CMOS 4th edition textbook I created the following schematic. This design will be used in my read/write portion of the circuit and be placed at the connection point of the 8-bit input/output.

Single Bit Sense Amplifier

Read/Write Circuit

Because this design will have separate read and write input/outputs a read/write circuit will be necessary. Below is the designed schematic using a symbol view of the sense amplifier shown above. As the project suggested, a single input read/write selection should be used for both read and write functionality so using a single inverter allows one input to control the sense amplifier for read capabilities and the NMOS device located at the 8-bit input for write functionality.

8-Bit Read/Write Schematic

The Register File Assembled

Once all these components were individually designed laid out and tested for design rule compatibility using DRC and LVS checks, they were combined together to form the final product. Below are the final schematic, layout, symbol and extracted views.

Final Master Schematic

Final Symbol View

Final Master Layout

Final Extracted View

Final DRC and LVS Confirmation

Simulation and Testing

The final design will now be simulated using different address inputs to verfiy proper read and write functionality. In each of the following simulations I will manipulate a small number of address bits to change between multiple addresses while manipulating the write bits to write multiple bit sequence of data to the addresses. Below is the simulation schematic and results with explanation of each.

Simulation Circuit Design using Project Symbol

Simulation #1

Simulation Results #1

In simulation #1 we manipulate the A[2] input bit and can see that we are writing to register address 27 and 31 decimal values of  0, 16 and 112. Each read/write sequence returns the proper written value and functions as expected.

Simulation #2

Simulation #2 Results

In simulation #2 we manipulate the A[3] input bit and can see that we are writing to register address 23 and 31 decimal values of  0, 4 and 16. Each read/write sequence returns the proper written value and functions as expected.

Simulation #3

Simulation #3 Results

In simulation #3 we manipulate the A[0] input bit and can see that we are writing to register address 30 and 31 decimal values of  0, 2 and 3. Each read/write sequence returns the proper written value and functions as expected.

Further Analysis 

Analyzing the power consumed by my device over a single simulation I took the average amperage provided by the 5v VDD source and found it to provide an average of 367.9uA at 5v. Using the formula below with an average current value found through simulating I determined the average power consumption to be relatively low as expected for a static RAM device. 

Using another method with the Cadence Virtuoso Calculator and the following function line I determined another value of 2.53mW for average power consumption.

Operating my device using a read/write period of 240ns gives a 4.16 MHz operating frequency. I did not test the device at higher operating frequnecy but further simulation testing could be performed to confirm at upper and lower end limit of operation frequency to avoid data corruption faults.

Conclusion

My design operated as expected with a slight modification involving the addition of a differential amplifier to sense the bit lines and avoid memory cell flip faults. This addition made the device more operational and functional but further work could be performed using a precharge circuit for the bit lines. I did not attempt this as this was my first attempt at designing a memory circuit. Each simulation performed as expected and my device was able to read and write data proving correct functionality.

All design files, layouts, schematics and associated simulations can be found in the .zip file attached below.
proj_f21.zip