Final Project - 32-word Register File

Final Project - ECE 421L

Author: Matthew Weishaar

weishm1@unlv.nevada.edu

Project description and goals:

Create a 32-word Register File

Lab:
In this lab we are going to create a 32-word register file with words that are 8-bit in size.

To start, we are not going to create everything in one large schematic all at once.
This would lead to a lot of headaches and unnecessary work.
Let's start with some basic components that are going to be crucial for our register file, and build upwards.

Let's start with our memory cell:

Memory Cell Schematic

Memory Cell Symbol

Memory Cell Layout Memory Cell Extracted

Memory Cell DRC

Memory Cell LVS

We can now use our basic memory cell to create the 8-bit word.

8-bit word schematic

8-bit word symbol

8-bit word layout

8-bit word extracted

8-bit word LVS 8-bit word DRC

Now that we have our 8-bit word finished, let's create our 5-input NAND for our row decoder.

We will not be creating a 32 word schematic, as we can do that in our final register file schematic.

5-input NAND schematic

5-input NAND symbol

5-input NAND layout 5-input NAND extracted

5-input NAND LVS 5-input NAND DRC

We can now use our 5-input NAND as the main component in our row decoder.
The row decoder is very important as it allows us to use a 5-bit input in order to access each of our individual 8-input memory cells.

Row Decoder schematic

Row Decoder symbol

Row Decoder layout

Row Decoder layout (zoomed in)

Row Decoder extracted

Row Decoder LVS Row Decoder DRC

We are almost there, we just need to combine our row decoder and our 8-bit memory cells to create our register file.

Register File LVS Register File DRC

Now that we finally have everything finished and LVS clean, we can test our design to prove it works as intended.

Register File Simulation schematic

In order to test our design, we are only going to have a singular bit of information be stored, and it will be shown in two addresses.

B<0> is the bit that is going to be assignmed to memory

row_choose is going to switch between word 0 and word 1 to test if our memory correctly gets assigned and

that it does not change when we do not have that row selected.

I0/I0<0>/I0<0>/mem is our first memory slot, word 0

I0/I0<1>/I0<0>/mem is our second memory slot, word 1

As you can see, after we start row_choose is high, all changes that occur to B<0> apply to word 1.

Once row_choose becomes low however, word 1 does not change based on B<0> and instead word 0 does.

This proves our register file can be edited only when that row is chosen, and that other rows are not changed.

Problems with project and potential additions or changes

The project is not perfect and there are many things that could be improved.

First off, let's start with and issues that arose and how those issues were addressed.
The bus declarations for our row decoder were long and could be shortened down, however

whenever the shortened declarations were attempted, the program would error.

There was also an issue when attempting to LVS the layout where netlists were merged, this is solved by connecting all vdd!.

Next let's talk about potential improvements

We could add read/write functionality. This would be useful so we may not accidentally write into critical information.

The memory cell layout could be more compact.

Overall, this project helped me understand basic chip construction and how it can be used to create certain devices.
I've constructed and used register files in previous classes, but only on the gate level, so doing it using transistors and creating a lot of
portions of it myself was really helpful.

As always I backup my project in zip on my computer and a separate flash drive.

lab_project.zip

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