Lab 6 - ECE 421L 

Author: Matthew Weishaar

weishm1@unlv.nevada.edu

Date: October 6, 2021 

Lab description and goals:

Learn how to create a NAND gate and XOR gate and use our created gates to make a full adder.

Prelab:

In this lab we will start off by creating a NAND gate and XOR gate.

	NAND	XOR
Schematic
Symbol
Layout
Extracted
DRC
LVS

We will then test these gates in a simulation to see if they are correct. Using the design from the lab we have:

We end up with this simulation:

Now that we have verified that our gates are correct, we can now use these in a full adder.

Schematic
Symbol
Layout
Extracted
DRC

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