Lab

Lab 5 - ECE 421L

Authored by Michael Velasquez

velasm4@unlv.nevada.edu

September 22, 2021

Lab description

Design, layout and simulation of a CMOS inverter

Prelab Content

The prelab of lab 5 had the students work through tutorial 3, which consisted of designing, simulating, and laying out a CMOS inverter.

The schematic of a CMOS inverter is shown below. This circuit consists of both a NMOS and PMOS transistor with dimensions of 12u/0.6u.

A symbol was then created from the schematic. The symbol is what students have learned a NOT gate to look like in CPE 100.

The layout of a CMOS transistor in the C5 process consists of a NTAP, PTAP, NMOS4, PMOS4, and M1_POLY as layed out below.

Connections between components were made in the metal1 and poly layer as shown in the screenshot below.

In order to prepare for DRC and LVS checks, pins for vdd!, gnd!, A, and Ai were made in the metal1 layer.

Once the layout was ready, students extracted the layout to prepare for the LVS check.

The screenshot below shows the LVS run directory; students were to compare the schematic and extracted view of their CMOS transistor.

My LVS check came back clean as both netlists matched in my design and layout.

To finish the prelab, students were tasked with testing the operation of their CMOS inverter. Unlike previous labs, the schematic was to include a no connection component to avoid floating node errors.

DC operating point simulation was to be used, but the voltage was to be swept from 0V/GND to 5V/VDD.

Results of the simulation are shown below. These results follow what is to be expected for a NOT gate.

Postlab Report

12u/0.6u CMOS Inverter:
The 12u/0.6u inverter is the same design, layout and simulations as shown in the prelab. In the lab, we simulated that inverter as it drives different value capacitances.

The test schematic is as shown below. No specific capacitance was assigned, as we will use that as a variable in simulation.

After launching the ADE, students were to choose a transient analysis over a span of 25ns.

As stated before, students were to sweep the value of the capacitor. This was done by using a parametric analysis and sweeping the "cap" variable from 100f to 100p by multiples of 10.

Results from the simulations are seen below.The smaller the capacitor, the closer the output follows the intended output of an inverter. This is because the larger capacitors take time to charge, which means the output won't change for a longer amount of time if there is a high cap value. The results follow this expectation, with a 100pC capacitor, the output hardly changes even though the input switches from gnd to VDD. With the 100fC, the output follows the intended output of a inverter.

The previous simulation was ran using SPECTRE, which is the SPICE simulator that students usually use in this lab. In this particular lab students were also asked to run the simulations in ULTRAsim, which can be used for larger circuits. The downside to ULTRAsim is that accuray is sacrificed in order to simulate more complex designs. For this particular device, the simulation results are identical.

48u/12u CMOS Inverter:
The second half of Lab 5 had students create a 48u/12u CMOS inverter. The process was nearly identical to the 12u/0.6u inverter, but the PMOS and NMOS transistor had a multiplier attatched to its design. Rather than simply extending the design, which would not be space efficient, students opted for a design using multiple fingers. With such a similar process, descriptions of multiple steps will be omitted. These steps are exactly the same to the steps shown above for the 12u/0.6u CMOS inverter.

Schematic:

Symbol:

The only difference between the two processes was present in the layout. As stated above, students were designing using NMOS and PMOS transistor with fingers instead of simply using long transistors. For the PMOS, odd numbered connections were the drain and connected to VDD while even numbers were the source and connected to the NMOS Transistor. For the NMOS odd number connections were the source and connected to the PMOS transitor, while even numbers were the drain and connected to GND.