Lab 3 - ECE 421L
The result of this sized rectangle is shown below.
Throughout this lab, when drawing on the layout screen it is expected that students are verifying their desing using the DRC check.
Cadence does not recognize this rectangle as a resistor, so using the RES ID layer, students must draw a rectangle of the same size and position.
In
order to connect to the resistor, n-taps must be added on either side.
This must be done in a way that covers the entire width of the resistor
is covered. For this instance, two pins in the n-tap is sufficient.
After labeling the pins, the resistor is done and can be checked. To do so, students extracted the layout view and analyzed the resistance. It is never perfect, so if the value is a bit off that is okay.
Once
a single resistor is designed, students were then instructed to create
a voltage divider. The tutorial called for a 1/2 voltage divider, but
for this lab students created a 2/3 voltage divider as shown below.
The final parts of the tutorial cover checking the layout design (both DRC and LVS), but this will be covered in the lab section of this report.
Lab Procedure
This lab has the students create a layout of the DAC which was created in Lab 2. The schematic is as shown below.
To do so, students took the voltage divider created in Tutorial 1 and copied it for each bit the input contained. For this lab we have a 10-Bit input so we must copy the layout of the voltage divider 10 times.
The
screenshots shown a few steps ahead of just copying and pasting. In
order to connect the voltage dividers, students used metal layer 1 to
create wires between desired terminals. This was done by using the same
rectangle function used in the prelab. If terminals were not connected,
but inputs or ouputs were needed, the same rectangle function was used.
To denote whether it was an input or an output, students would select
the node and edit the properties using hotkey Q. The inputs and outputs
must match the schematic exactly. This will ensure that once the LVS
check is ran the netlists match.
Once
wires and nodes are drawn on the layout view, students created pins
with the same name as the pins shown in the schematic. If names do not
match, neither will the netlist. This name is especially important for
the ground terminal. The schematic an layout must both be named "gnd!"
which denotes a global value.
Once all wires are drawn and pins are created it is time to check the layout view. A DRC check is ran to ensure the layout view follows all the design rule constraints.
If no errors are found, students must extract the layout view.
The final check is to run LVS and compare the extracted layout and the original schematic.
After clicking run, a new window will pop up telling the user whether the LVS was completed or not.
This window does not show the full details of the matching net-lists, so students must check the output by clicking "output" shown on the Artist LVS screen shown two steps prior.
This pop shows any errors or mistakes that may have been made throughout the process.
Once the students go the netlists to match, the lab has been completed.
In my lab directory I have zipped my library under Lab 2 (as this lab was an extension of the previous lab).