Lab 2 - ECE 421L 

Authored by Michael Velasquez

Email velasm4@unlv.nevada.edu

September 1, 2021

 
Lab description

 Design a 10-Bit DAC


Prelab

For the prelab, students were given a schematic contaning an digital to analog converter to analyze and understand before class.

The schematic below contains the symbol view of both a ADC and a BAC which is used to convert a given analog signal to a digital signal.


The simulation for the given schematic is as shown below. The input is a clean sinusodial wave pattern, and the output is a sequence of steps that follows the input wave.


While the input and output are only shown, that is not the signals that are needed to be worried about in this circuit. The input signal is fed into an ADC and converted to a 10 bit binary signal which cannot be read by most devices alone. This 10 bit binary number must be interpreted in a usable way, which is what the DAC is used for. A DAC is a series of voltage dividers used to translate a set of bits into an analog signal. The steps in the output signal are based on the bits set to VCC while it is being interpreted.

This signal is a set of 10 bits, of which are arranged from least significant to most significant. In order to analyze the output signal, we must calculate what the least significant bit (LSB) is. This is done using the equation
LSB=VDD/[2^N]
VDD is determined by the designer. For this lab, VDD has been set to 5, but in practical usage it can be set to any value. N represents the amount of bits being interpreted. For this lab N is set to 10, but again that can change based on the designer's input.
(5V)/[2^(10)]=4.89mV
Therefore, the LSB is calculated to be 4.89mV.

The more active bits found in the input, the more steps are present in the output voltage. If only the least significant bit is active, then there will be one step between the peaks of the input voltage. This is shown in the simulation below. The input voltage is set to a 5mV amplitude, so as expected, there is only one step between the peaks.



Lab

In the lab portion, we must design and implement a 10-bit DAC.



First step is to design a voltage divider which is the basic building block to this circuit. Below we see a 2/3 voltage divider which will be used to interpret a single bit of data.


A symbol is then created from the voltage divider so that we can easily stack them to create our 10-bit DAC. The pin labeled "in" takes in the bit of data. Pin "out" is fed into the next voltage divider, while "bottom accepts data from the voltage divider below.


Shown below is the 10-bit DAC made by arranging 10 voltage dividers. The input pins are labeled B[9:0] in order to receive a 10 bit signal. Below all of this is a 10k ohm resistor which completes the 2R/R DAC.



This circuit has an output voltage, which is calculated below. Even with all the resistors present in the cascading voltage dividers, the output voltage of B9 is R



Creating a symbol of this schematic leaves us with what is shown below, but students were expected to have the same footprint as Dr. Baker's example. In order to do this, students were to delete this symbol and copy in Dr. Baker's drawn symbol.


After completing the copy and paste function, students are left with the below symbol. This is an exact copy of Dr. Baker's footprint.


That symbol is then tested by connecting the 10-Bit DAC to a load of 10pF, and grounding all input bits but B9.


The expected time delay (the time where the output voltage is expected to reach 50% of the final value) is calculated below using the equation Td=0.7RC.




The expected time delay of this simulation is 70ns, which matches the output given by Cadence Virtuoso.


The students' work was then tested by inserting our newly created symbol into the schematic given in the prelab. If the 10-Bit DAC was created correctly, the output should closely match the simulation provided in the prelab work.


The simulation results below proves that the 10-Bit DAC was designed and layed out correctly. The output is a series of steps that closely follows the input voltage.


The 10-Bit DAC was then tested by attaching a  10K load to the output.


When a 10K

Explain what happens if the DAC drives a 10k load?
With the calculated output resistance being 10k, this load essentially turns into another voltage divider, with the output resistance and the load resistance being equal. It is expected that the output voltage will then drop by 1/2. The simulation below shows that this assumption is correct.


The figures below show the schematic and simulation of our system with a 10pF load.


he figures below show the schematic and simulation of our system with a 10pF and 10K RC load.


In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). Discuss what happens if the resistance of the switches isn't small compared to R.
If the resistance of the switches weren't small compared to R, the resistance would be added in series to each voltage divider. This higher impedance would lead to a higher output resistance, meaning the voltage drop across the resistance would be much higher.

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