Lab Project - ECE 421L 

Authored by Your Michael Velasquez,

Email: velasm4@unlv.nevada.edu

November 23rd, 2021 

Lab description

Project – design a register file (RF) that uses an 8-bit word and has 32 words. The RF uses a 5-bit 

address to access the 32 8-bit words. Other inputs to the RF are the 8-IO lines for reading and writing, a control signal, RW,

for indicating either a read or write to the RF, and VDD/ground.

To start this project, we must first design a base 1bit memory cell. This memory cell must only be written to if this adress is being called, so the inputs for this cell must be D, Di,and a Row line which determines when this cell is being written to. To ensure that the value is kept the same, two inverters are placed between the D and Di values of a small width. The row line is attatched to the body of two NMOS transistors. This means that when the row line is active the value of D and Di can be written into the cell. When the row line is no longer active, the values are kept as the left and ride ports of the inverters must be kept opposite. The equal number of transistors ensures this is being kept true and constant. If there were an odd number of transistors, these values would continously oscillate. This design is implemented below with a transistor level schematic. The inverter was laid out previously in lab 5, thus the scematic was omitted.

Below is the symbol of the memory cell. There is only inputs as it is only meant to be written to as per Dr. Bakers edited instructions.

Below is the layout of the memory cell. It consists of two inverters and two NMOS devices.

The layout meets all of the DIVA Rule requirements, and a clean DRC check is shown below.

The memory cell layout was extracted so that students could LVS check their design.

As shown below, the layout and extracted view match the schematic. LVS results show that the netlists meet every requirement.

In order to ensure logic functions are correct, every component was tested along the way. The test schematic for the memory cell is as shown below. An oscillating input as placed on the D input to show that the data can be written in multiple instances rather than just a static "1" or "0" input.

The results of the test simulation are as expected. When the row line is a logic "1", D is passed to the memory right net.This can be seen between 0 and 12ns. When row line is logic "0", the memory right net keeps a static value. This can be seen between 12 and 22ns.

For our register file, we need an array of 8-bit memory cells. To design this, we must link eigt of the previously designed memory cells. Each cell in intended to receive unique inputs, so we introduce eight D and Di inputs. To keep a neat design and workspace a bus was used. This allows students to setup eight memory cells without copying that many symbols. The row input is kept as a single node, as the row line will come from our decoder and is meant to address a whole 8 -bit word.

The symbol for the 8-bit word is as shown below. Again, only inputs are being show as the memory cells are only meant to be written to.

The layout of the 8-bit memory cell was completed by instantiating eight 1-bit memory cells and linking them.


Our layout passes the DRC check.


Layout was then extracted so students can LVS check their work.


Extracted layout is LVS clean, thus matching the schematic.


To test the 8-bit memory cell, eight DC voltage sources were attatched to the inputs of our symbol. The row line was then set to VDD to allow these inputs to be latched into their respective memory cells.


The simulation resultsare as shown below. Glitches are shown at a small scale. This can be caused by the use of inverters to keep lasting memory. Any noise may cause the inverters to begin oscillation, but the even number prevents this and the value returns to the intended value.




Now that the 8-bit words have been completed, students must design a 32-bit row decoder to handle addressing. In order to get 32 addresses students need to have a 5-input NAND gate as the basis of their decoder (2^5=32).

The schematic of the designed 5-bit NAND gate is shown below. All inputs must be logic "1" to get a grounded output, so five NMOS transistors are placed in series with ground and the outputs on either end. For any other five inputs, the output is pulled up to logic "1", so the parallel PMOS transitor ensures any low input will draw the output high.


The symbol for the designed NAND gate matches what was taught in CPE 100.


The layout for the 5-bit NAND gate is shown below. The inputs are staggered to ensure that connections for the projects final layout can be made cleanly.


Layout follows all of the DIVA design rules, which yields a clean DRC check.


Layout was then extracted so that a LVS check can be made.


LVS check came back clean, as the netlists between extracted layout and schematic match.


To design a 5-bit to 32-bit decoder, 32 NAND gates were required. In order to keep a clean schematic, busses and arrays were used. This meant that the five input busses must be labelled in a way that ensures "00000" to "11111" matches its respective bus. "00000" must drive the 0th instance low and "11111" must pull the 31st instance low. These outputs are then inverted so that when the final output is connected to the row line, the addressed word is able to write.


The symbol for the row decoder is as shown below. Five input bits labeled A0 to A4 are the inputs, with 32 row lines being the output.


The layout was too large to be displayed, but the first instance's layout is below. The five inputs are fed through an inverter and all of those output lines were dragged down parallel to the 32 NAND instances. Every instance then has five of the outputs pulled that matches its assigned address. The first instance has an addres of "00000", so A0i, A1i, A2i, A3i, and A4i are pulled to the NAND inputs. This ensures that once these inputs are sent through the NAND and inverte, our row line will be pulled to VDD.


The layout is DRC clean.


Extracted view of the layout is as shown below.


The schematic and extracted layout have matching netlists.


To test the row decoder, a pulse source is attatched to A0 and all other inputs are tied to ground. This will mean that only two row lines will be oscillating in the results, but every address should function correctly as they were all wired the same.


Simulation results are as intended. When our input is high, row line one is as well. When the input is low, row line 0 is active.


All of the necessary components are now completed. All that is left is to design the completed register file. To do this, student connected the output of the row decoder to the row line of the 32 8-bit memory cells. Other inputs include D(i)<7:0> which are attatched to every 8-bit memory cell, and the five address inputs.


The completed schematic with initials is shown below.


Once again, the final layout of this design is too large, so only the first to instances are shown. The layout is organized so that the signals are flowing from left to right. Initally, the address input is sent through the inverters, then passed to the row decoder. The row decoder then sends a logic "1" signal to a single 8-bit memory cell which is located all the way to the right of the layout.


The layout passes DRC check with zero errors,


An extracted view of the layout was created to LVS check the design.


Both schematic and extracted layout of the final RF design have matching netlists.


Finally, the register file is tested to ensure it functions as intended. For this simulation, only two addresses are being called. These addresses are "00000" and "00001". To test these two, both instances one and zero are to be probed. We are using a pulse source set to D<0> to test the 0th memory cell of both addresses. Initially a read write line was to be used so that we can have outputs being read, but the project has since been changed so that we merely probe these lines.


The simulation results are as intended. A time of 40ns was uses, so these signals have significant charge and discharge times due to the scale. As the adress bit (labled net) changes,  so does R<1:0>. When net2 is high, we are adressing "00001", so this allows instance one to be written to. This can be seen from time 1 to 12ns as I1 follows D<0> in this timeframe. Alternatively, from time 12 to 22ns, I0 follows D<0> as the 0th instance is being addressed.

This concludes the design and testing process of the Register File.

EE421L_PROJ.zip

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