Lab 2 - ECE 421L 

Authored by Brandon Staffieri

staffier@unlv.nevada.edu

September 01, 2021

Lab Description

Design of a 10-bit digital-to-analog converter (DAC)

Prelab Content

Prior to this lab session, we were tasked with downloading a provided lab2.zip file (containing a simulation example that uses an ideal 10-bit Analog-to-Digital Converter and Digital-to-Analog Converter). We had to upload this file to our design directory on the csimcluster server and unzip it, followed by adding a library definition for it in the cds.lib file so that it is properly recognized. We then used Cadence Virtuoso to view and simulate the schematic with a 1 second transient analysis that allowed us to observe the behaviour of the circuit.

As shown in the schematic, Vin is an analog input and B[9:0] is simply the converted binary/digital representation of that value which the ADC spits out. Additionally, we were asked to explain how to determine the least significant bit of the converter, which is the minimum voltage change on the ADC's input that will result in a change in the digital code B[9:0]. The following image was provided in the lab document and includes the necessary formula.

   
As can be observed in the above image, the formula to calculate the Least Significant Bit is LSB = (VDD)/(2^N). In the case of our circuit, we are using a 10-bit bus and have provided a value of 5 volts. Thus, the calculation would be LSB = (5V)/(2^10) which is approximately 4.882mV.
To display this more clearly, as the original simulated result has far too many steps in the output voltage for this behaviour to be observed, I have provided an alternate simulation that uses a 2.5mV input with 2.5mV offset.


   
Postlab Report
This lab consisted of us creating multiple schematics and symbols in Cadence Virtuoso in order to create and simulate a 10-bit DAC. As I completed each step, I took a corresponding screenshot. Those of significance can be observed along with descriptions as follows:

As the main goal of this lab was to design a 10-bit DAC using an n-well resistor of 10k, the obvious first step was to create the schematic and symbol for said resistor. In this case, it is a voltage divider using three 10k resistors.


   
Next, I created the schematic for the 10-bit DAC by instantiating this newly created symbol ten times along with adding a 10k resistor to ground and labels for Vout and the ten input pins (B0:B9). As with the resistor schematic, I turned this schematic into a symbol once it was completed. As per the recommentation in the lab document, I copied Dr. Baker's Ideal_10-bit_DAC symbol view to a Mydesign_10-bit_DAC cell in order to maintain an identical footprint for my 10-bit DAC symbol as in his provided design.


   
Here, I did hand calculations to show the method for calculating the overall resistance and voltage values. In my example, I only used two inputs; however, the same principal will apply for the overall resistance when using ten inputs as there is no difference between one and nine inputs being tied to ground (the parallelization process will just be repeated). I also hand calculated the delay

, and then I created and simulated a schematic to verify that delay.



   
Then, I copied the provided sim_Ideal_ADC_DAC schematic and replaced the ideal 10-bit DAC with the 10-bit DAC that I designed in order to verify that the design functions correctly. I simulated this with a transient analysis to illustrate the proper operation of my DAC. I did run into convergence problems during simulation, so I followed the advice at the end of the lab document to force the simulation to converge by adjusting the tolerance options.



   
Regarding MOSFETs
"In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). Discuss what happens if the resistance of the switches isn't small compared to R."
In this case, the resistance of the DAC would increase and there would be a greater voltage drop between the ADC and DAC, resulting in a lower output votlage.
   
Return