Lab Project - EE 421L 

Authored by Jimmy Ruangnol

(ruangnol@unlv.nevada.edu)

November 17, 2021

Lab Project Description

• For this project design a register file (RF) that uses an 8-bit word and has 32 words.

• The RF uses a 5-bit address to access the 32 8-bit words. 

• Other inputs to the RF are the 8-IO lines for reading and writing, a control signal, RW, for indicating either a read or write to the RF.

• Have VDD/ground inputs.

Creating Register File Components

SRAM

The first component of the RF is to create a single bit SRAM cell. 

It is composed of (1.5u/1.5u) inverters.

A data input, data ouput, and row line. 

The smaller transistors will allow for a faster switching speed, regardless of "1" or "0", the data will pass through the NMOS and constantly update the SRAM.

Below is the SRAM schematic: 

SRAM Schematic

Below is the SRAM symbol:

SRAM Symbol

Below are the SRAM Layout and Extracted:

SRAM Layout	SRAM Extracted

Below are the SRAM DRC and LVS:

SRAM Schematic

SRAM Simulation

SRAM stores value when Row is high. 

8-Bit SRAM or Word 

The next step in the project is to create a 8-bit SRAM cell by combining 8 1-bit SRAM cells. This will create 1 word

Below is the 8-bit SRAM schematic: 

8-bit SRAM Schematic

Below is the 8-bit SRAM symbol:

8-bit SRAM Symbol

Below are the SRAM Layout and Extracted:

8-bit SRAM Layout

8-bit SRAM Extracted

Below are the 8-bit SRAM DRC and LVS:

8-bit SRAM Schematic

8-bit SRAM Simulation

8-bit SRAM stores value when Row is high. 

5 Input NAND GATE 

We will create a 5 input NAND gate as a subsection of the row decoder. 

This NAND gate is needed to obtain uniques addresses throughout the 32 word array.

Below is the NAND Gate schematic: 

NAND Gate  Schematic

Below is the NAND Gate symbol:

NAND Gate  Symbol

Below are the NAND Gate Layout and Extracted:

NAND Gate  Layout	NAND Gate Extracted

Below are the NAND Gate DRC and LVS:

NAND Gate  Schematic

NAND Gate  Simulation

From the results, we can see that as the gate runs "high" all outputs will be "0".

5 Input AND GATE 

Our NAND gate but with an inverter at the end.

Below is the AND Gate schematic: 

AND Gate  Schematic

Below is the AND Gate symbol:

AND Gate  Symbol

Below are the NAND Gate Layout and Extracted:

AND Gate  Layout

AND Gate Extracted

Below are the AND Gate DRC and LVS:

AND Gate  Schematic

AND Gate  Simulation

From the results, we can see that as the gate runs "high" all outputs will be "1"

32 Word Array 

Next we instantiate th 8-Bit word cell or SRAM eight times to create a 32 Word Array. 

The 32 Word array is going to be our memory storage for the Register File. Each row can be read by using a row decoder to turn on that row.

Below is the 32 Word Array schematic: 

32 Word Array Schematic

Below is the 32 Word Array symbol:

32 Word Array  Symbol

Below are the 32 Word Array Layout and Extracted:

32 Word Array  Layout	32 Word Array Extracted

Below are the 32 Word Array DRC and LVS:

32 Word Array  Schematic

32 Word Array  Simulation

32 Word Array stores value when Row is high. 

Row Decoder 

A large component of the register file is the row decoder.

The row decoder will determine which of the 8-bit word cell will be turned on.

There are 32 possible addresses to choose from.

Address:

Below is the Row Decoder schematic: 

Row Decoder Schematic

Below is the Row Decoder symbol:

Row Decoder  Symbol

Below are the Row Decoder Layout and Extracted:

Row Decoder  Layout	Row Decoder Extracted

Row Decoder  Top

Row Decoder  Bottom

Below are the Row Decoder DRC and LVS:

Row Decoder  Schematic

Row Decoder  Simulation

When the inputs of A,B,C,D,E is "1" then the address then Row 31 turns on.

Register File 

The Register file is the combination of all the components worked on this project. The Read/Write input signal is added to determine were the RF reads "1" or writes "0". This will also separate the outputs by running it through NMOS's.

Below is the Register File schematic: 

Register File  Schematic

Below is the Register File symbol:

Register File  Symbol

Below are the Register File Layout and Extracted:

Register File  Layout	Register File Extracted

Below are the Register File DRC and LVS:

Register File  Schematic

Register File  Simulation

Conclusions

To make this simulation more cleaner, the original design would need capacitors throughout the circuit to properly power each components without delay.

The simulation must have a  high enough pulse width to be able to read and write the data inputs from the row decoder. 

The Design is functional to its basic operation, but further improvements can be made to better the outcome. (Increasing power distribution).

Project Files are Located Here

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