Lab 3 - EE 421L 

Authored by Jimmy Ruangnol, 

(ruangnol@unlv.nevada.edu)

  

Today's date is 09/07/2021

 

Lab Description

 

The purpose of this lab is to design a 10-bit digital to analog converter and record its function. We will also be designing a DAC using n-well resistors. The function of a DAC is converting a a digital binary number to an analog output signal. We will be designing the layout version of the DAC.

 

Prelab

 

Back up the work from lab 2  by emailing yourself.

Lab

 

Resistor:

 

We will be starting the lab by creating a 10Kohm n-well resistor using a sheet resistance of 800Oohms/square. 

 

We will be using a lambda of 0.3um for this process. The minimu width of an n-well defined in CMOS design rules is 12*lambada = 3.6um.

 

The formula for a resistor is R = r(L/W) where R is total resistance and r is the sheet resistance. Therefore (10Kohms/800ohms)*3.6um = 45um.

 

We will be laying out our resistor in metal1 layer using N-Well and res-id. Press "R" for each material and drag for a rectangular shape. 

 

 

 

We will now preform a "DRC" for this resistor and then extract the layout to see the final resistance. 

 

 

1-Bit-DAC:

  

We will now be creating a section of the DAC called the 2R_R. The schematic will be the blueprint for out layout version, and we will be using the 10Kohm layout resistor by pressing "i" to instantiate. Do not forget to create your input and output pins in the layout; it must match what the schematic states. 

 

 

We will now preform an extraction on the layout and then a LVS verification for the 1-Bit-DAC. This will ensure less issues in the future.

 

 

10-Bit DAC

 

After the LVS of the 1-Bit-DAC we are ready to create the layout version of the 10-Bit-DAC.


The layout version the the 10-Bit DAC will have a similar process as the 1-Bit-DAC. We just have to make sure the connections match the schematic to prevent further issues.
 

Then we will have to perform an LVS on the DAC.

After the exatraction of the 10-Bit DAC layout we will now perform an LVS on the 10-Bit DAC schematic and extracted file.

 
The layout passes the LVS and DRC standard. We will now send a back up to ourselves for safety reasons.
 


lab2-3 zip file
 




 


 

  

 

 

 

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