Lab 7 - EE 421L
Authored
by Ricardo Rodriguez
UNLV E-mail: rodrir15@unlv.nevada.edu
November 3, 2021
Prelab Work:
- Backed up all work presented in lab by zipping the FTP folder and emailing the new file to myself
- Tutorial 5
A ring oscillator without the use of arrays/buses
A ring oscillator with the use of arrays/buses
Symbol and schematic for simulation
![](prelab/sim_ringosc_schem.png)
Simulation Results
![](prelab/ring_osc_sim1_graph.png)
Simulation of
the ring oscillator without using initial conditions
Simulation of
the ring oscillator using initial conditions (output/input is 0)
We can add our inital condition by going to Simulations > Convergence Aids > Initial Conditions
Now, to create the layout of the ring oscillator
We
connect 2 inverters together and then delete the 2nd inverter to copy
the remains and make it easier to create 31 stages
![](prelab/ring_osc_layout_postcopy.png)
We can then connect our output to our input to create a feedback loop by connecting them to Metal2 by via
![](prelab/ring_osc_layout_m2Conn.png)
and
then we can connect our pins, but our LVS will fail as the schematic
does not have a pin for osc_out, so we have to add it in
![](prelab/ring_osc_Array_adjustLVS.png)
If we LVS again, we will see that it matches and we can run the simulation off of our extraction
![](prelab/sim_ringosc_extracted.png)
Lab Work:
For
the lab we create a 4 bit inverter, an 8 bit inverter, OR, NOR, AND,
NAND gates. This is done by the use of buses rather than creating many
instances of gates
4 Bit Inverter:
Schematic
![](lab/inv_4bit.png)
Symbol
![](lab/inv_4bit_symb.png)
Simulation Schematic and Sims
![](lab/inv_4bit_sim.png)
8 Bit Inverter:
Schematic
![](lab/inv_8bit.png)
Symbol
![](lab/inv_8bit_symb.png)
Simulation Schematic and Sims
![](lab/sim_inv_8bit_graph.png)
8 Bit NAND:
Schematic
![](lab/nand_8bit.png)
Symbol
![](lab/nand_8bit_symb.png)
Simulation Schematic and Sims
![](lab/sim_nand_8bit_graph.png)
8 Bit AND:
Schematic
![](lab/and_8bit.png)
Symbol
![](lab/and_8bit_symb.png)
Simulation Schematic and Sims
![](lab/sim_and_8bit_graph.png)
8 Bit NOR:
Schematic
![](lab/nor_8bit.png)
Symbol
![](lab/nor_8bit_symb.png)
Simulation Schematic and Sims
![](lab/sim_nor_8bit_graph.png)
8 Bit OR:
Schematic
![](lab/or_8bit.png)
Symbol
![](lab/or_8bit_symb.png)
Simulation Schematic and Sims
![](lab/sim_or_8bit_graph.png)
Next,
we had to work on a MUX. A MUX allows us to choose an input based off
of our selection input. It maintains the equation Z = A*S + B*Si
A DEMUX works in the opposite way. Based on our input, (z in this case) we can choose either A or B based off of our S and Si
Operation of a MUX.
Schematic to simulate the MUX
Simulation of the MUX
![](lab/sim_mux_2bit_graph.png)
Now we create an 8bit MUX like the following
![](lab/mux_8bit.png)
with this symbol (our Si is built-in)
![](lab/mux_8bit_symb.png)
We can simulate our 8 bit mux like this
![](lab/sim_mux_8bit_graph.png)
The next part of the lab is to create an 8bit adder. We do this by starting from the beginning
Schematic for a 1bit adder
Symbol for the full adder
![](lab/full_adder_symb.png)
An 8 bit
adder using buses and arrays
Symbol for the
8bit full adder
![](lab/ripple_carry_adder_8bit_symb.png)
Simulating the adder by adding
A:00000001 and
B:00000001
Our output is
Cout:0 Sn:00000010
![](lab/sim_FA_8bit_graph.png)
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