Lab 5 - EE 421L 

Authored by Ricardo Rodriguez

UNLV E-mail: rodrir15@unlv.nevada.edu

October 6, 2021

Prelab Work: 

• Backed up work by zipping the files in the ftp and emailing it to myself
• Went through Tutorial 3
• Schematic and layout of a 6 micron wide inverter

• Simulation of the inverter schematic

• Simulation of the inverter extracted layout

Lab Work:

For the lab, we created two different types of inverters. For the first inverter, we have a width of 12u/6u for the pmos and nmos respectively.

For the second inverter, we have a width of 48u/24u for the pmos and nmos respectively.

   48u/24u Inverter schematic:                      Symbol                                                              Layout of 12u/6u Inverter:                     LVS Results:
                                                          
Simulations for the 48u/24u inverter when connected to 100ff/1pf/10pf/100pf capacitor respectively:
 

The created Lab 5 directory can be found here

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