Lab 3 - EE 421L
Authored
by
Ricardo Rodriguez
UNLV E-mail: rodrir15@unlv.nevada.edu
September 15, 2021
Pre-lab:
- Backed up data by zipping up the folder on a local file and emailing it to myself
Note:
I reworked the schematics of the DAC to a similar fashion of
Dr.Baker recommended. The new schematics are on the images below.
Lab Work:
Tasks
- Use the n-well to layout a 10k resistor as discussed in Tutorial 1
- Discuss, in your lab
report, how to select the width and length of the resistor by
referencing the process information from MOSIS
To create a 10k n-well resistor (assuming a tolerance value of 5%), first we must know that sheet resistance of our material.
For
our case, the sheet resistance is 800 Ohms/ Sqr. We can determine the
length and width of our resistor by finding our value l, which is
length/width.
Since
we want a 10k resistor, and our minimum width is about 3.6 micron, we
can round our length up to 4.5 micron (keeping in mind that it has to
be a 0.15 micron multiple). Deriving our Length is nothing more than R*W/Rsqr, which was roughly 56.25 (we put in 56.1) micron.
The extracted value of our resistance is 10.21k Ohms, which is within our +/- 5% tolerance.
- Use this n-well
resistor in the layout of your DAC
- Discuss, in your lab
report, how the width and length of the resistor are measured
- Ensure that each
resistor in the DAC is laid out in parallel having the same x-position
but varying y-positions (the resistors are stacked)
- All input and output Pins should be on metal 1
A R-2R bit
Array of
R-2R bits, creating a DAC
The
width and length of our resistors are measured by the measurement tool
('K'). We measure from the only the n-well section and ignore
the
pin section as it has no impact on our resistance, because it is about
the same width as the resistor. We can see this in the extracted view
of our single 10-k resistor.
We
created an array of 2-R2 bits and end up creating our DAC which is on
the image on the right up above. Our bits are stacked by a difference
of
45 micron in the y-direction and are 60 micron from the layout origin.
We did this by copying a single R-2R bit and pasting them by the array
option
of the copy tool (Not the mosiac). If zoomed in, it is seen that all of
the pins and connections are on the metal 1 layer.- DRC and LVS, with the extracted layout, your
design (show the results in your lab report)
Our LVS of our DAC schematic and the extraction of our DAC layout. It shows that they match in function. - Zip up your final design directory and place it in the lab3 directory,
with a link on your lab report, so the grader can examine
both the layout and schematic (and simulations)
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