Lab 2 - EE 421L 

Authored by Ricardo Rodriguez

UNLV E-mail: rodrir15@unlv.nevada.edu

Due: September 8, 2021

  

Design of a 10-bit digital-to-analog converter (DAC) 

Pre-lab Work:

         

To understand how the ADC functions, there had to be some experimentation with different inputs and outputs.

When simulated as was given, the peak voltage of Vout was about 4.995V rather than the 5V, like Vin has. 

       


         

The first thing I tested was to see how Vout would respond to Vin without the DC offset of 2.5V.

What is seen is that whenever Vin goes below 0V, there is no output for Vout. Vout is only non-zero

when Vin is above 0V.

          

     

My next question was how does Vout get the values and how is it correlated to the values of B[9:0]  on the

ADC and DAC. I made another DAC with its own separate output, called Test. With it I tested different values along

the inputs of B[9:0]. Here are a few of the simulations.  

       

     

    

   
   
     Testing schematic
    
     
    
      
     
    
         
       

     

      

      

       

        
     Simulation for B9 = 5V and the rest 0V

     Test = 2.5V     
      

      

     

     

              

       

    

      

      

       

        
     Simulation for B0 = 5V and the rest 0V
     Test = 4.88mV

        

        

         

      

        

From these two simulations, we can see that the output of Test with relation to B[9:0] is nonlinear.

Instead it is actually inversely proportional given by the equation Test = Vin/2^n where Vin is the

magnitude of our voltage and n is the 1-10, with respect to B9-B0. For the above images,

5/2^10 = 4.88mV and 5/2^1 = 2.5V, which is correct.

     

What the DAC will do with multiple logic 1's is add them together. For example, if we re-run the
initial simulation, but never allow B4 (or n=6), we will get 4.995V - (5/2^6) = 4.917V (with
rounding error) for our peak voltage where all of B should be logic 1. The reason why the
output should be 4.995V and not 5V is because the addition of all 5/2^n, for 1<=n<=10, can not
reach up to 5 and the upper bound would need to approach a higher number, but there would
be too many pins on the ACD and DAC chips and wouldn't be practical.
       
     

       

The ADC works in the opposite of the DAC. Rather than add up different values of 5/2^n, the ADC will instead
break up a signal into components of 5/2^n. An example being that a signal of 3.75V will be broken into the
components of 5/2^1 and 5/2^2. On the chip, this means that the outputs B9=B8=5V, while B[7:0] = 0V.

     

   

     

     

Lab Work:

      

    Design of a 10-bit DAC:    

     

             

       Full View                    Bottom Half                             Top Half

       

       

     How to find Vout of the DAC:    

You can find the value of Vout by determining the values of all inputs. You will use superposition on each input. Since we will consider the inputs

of the DAC as voltage sources, we will ground all inputs, except the one we are analyzing. We combine all the resistors in series as a value of 2R. 

As we approach the MSB (most significant bit), we will be putting the combined resistors in parallel with the resistors that go to ground. 

If we can no longer combine resistors, we can thevenize the circuit where we have the voltage source and then find the value of Vout. 

       

       

      Symbol View of the DAC schematic:    
             
We can create a symbol and go into a symbol view by going under Create -> Cellview -> From Cellview
from the schematic view of the design we want to create a symbol for.
     
       
       Simulation of the designed DAC (NO load):
         
         
               
                         B9 is Vdd                                     B9 and B6 is Vdd                          B9, B6, and B1 is Vdd
                       Vout = 2.5V                                      Vout = 2.8125V                               Vout = 2.82V
We can figure out the value of the our output by summation of 1/(2^n) multiplied by the value of Vdd.
For example, where B9 is Vdd, Vout = 5(1/2^1) and the third simulation is Vout = 5*((1/2) + (1/2^4) + (1/2^9))   
             
       
         Simulation of the DAC with a load (R = 10k and a capacitance of C = 10pF):
Note: Only B9 will be "active" while the other inputs will be grounded for the following simulations and will start at 500ms

          No Resistive load and have a 10pF capacitor:
                   
Our estimated time delay will be determined by Td = .7RC= 0.7(10k)(10pF) = 70 ns.
Looking at the simulation, we can see that Vout is at it's halfway mark of 1.25V at time roughly 69.78ns, which is incredibly close to
the calculated delay of 70ns.
         
         
           No capacitor and have a 10k resistive load:
                 
 Note: The change in Vout has no delay with relation with Vin, given it has no capacitance but a
different final Vout of 1.25V
           
           Both capacitor and a 10k resistor, in parallel:
               
Note: Has a delay of 70ns and a final Vout of 1.25V.       
     
            Symbol placed in the example schematic from the pre-lab:
                    
Note: The simulation shows the same function as the DAC from the pre-lab.  
       
         

    What happens if the switches in the schematic has a high value of resistance relative to R:

If we take into account the internal resistance of a switch with comparable resistive values relative to R,

the final Vout will be smaller since it will take more work/voltage to go through the internal resistance

and "give less" for our device. 

In other words, this is shown by V=IR. Since the current will be the same going into 2R of a 

switch's "branch", the 2R needs to be higher than the Rinternal since we will be getting a voltage divider of

(2R/(2R+Rinternal)).

        

            

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