Lab 6 - ECE 421L 

Authored by David Pinales,

Today's date: 10/17/21

Email: pinales@unlv.nevada.edu

Lab description:

upon the lab, we first will need to complete tutorial 4

Prelab:

For the beginning, Create the following schematic for a nand circuit, then check for any errors.

Once successful, we then move towards creating the nand symbol:

After saving and checking the symbols parameters, we then proceed to draft a circuit for the symbol and simulate:

(Launch ADE -> setup correct settings -> Simulate)

Simulation:

From the given simulation, The NAND gate correctly shows the desired output with Input at 5V the output is driven to 0V.

Now, Creating the layout:

Layout of NAND w/ DRC check:

Extracted Layout:

LVS Check of layout:

Finally, this ends our demonstration of tutorial 4 and Prelab!

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Lab 6

Experiment 1: Draft the schematic of a 2-input NAND gate using 6u/0.6u MOSFETs and create layout and symbol views and show the cells DRC and LVS without errors. Simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10 and 11)

Now we establish our new library, Lab6, with the given cell name “nand2_L6”

Schematic:

Create Symbol:

Layout w/ Extracted, DRC & LVS:

Next, we simulate the NAND gate with the correct logical operation:

Truth table:

A	B	A nand B
0	0	1
0	1	1
1	0	1
1	1	0

Schematic of Simulation:

We need different parameters, each for the voltages pulses:

*Note: Must add the model libraries to simulation

A ->

B ->

Simulation:

At the end, we have the finishing result with the given parameters giving us our desired Truth table.

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Experiment 2

Creating the 2-Input XOR Gate

First, we create our new cell labeled “xor_DAP_L6” also with the given schematic.

Schematic w/ Check:

Symbol:

Now, We have our layout:

Layout:

Extracted/LVS:

Now we simulate the XOR gate with the NAND gate and inverter.

Parameters:

A ->

B ->

Results:

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Experiment 3

Full Adder

Schematic:

Symbol:

Layout:

Simulation of Full Adder:

Parameters:

Results:

This is the end of the lab 6.

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