Lab 5 - ECE 421L 

Authored by David Pinales,

Today's date: 10/1/21

  Email: pinales@unlv.nevada.edu

For this lab, a demonstration of my knowledge through CADENCE will be conducted on a CMOS inverter.

Prelab: From the given prelab, through the previous guided tutorial 3 we created an inverted circuit using the previous labs PMOS and CMOS. After the given steps we have the following:

Using this the schematic as our guide, we then implement a Create->Cell view-> From Cell view. To get the following symbol

From the given symbol, a layout is now created:

Once the layout has passed it initial tests (verify -> DRC) then, an extraction of the layout is preformed:

Based on the given schematic, now we then implement from the previous symbol used and perform the following simulation from the created circuit:

With the following results:

Simulation w/out VDD

This, of course, is not the results we are needing so,

Simulation w/ global Valve:

Following the result with the needed parameters our final results are from the following picture above.

LAB 5:

Experiment 1:

In this experiment, a demonstration in making a 48u/24u inverter & a 12u/6u inverter is performed for the following results:

12u/6u Inverter Schematic:

*Check: No Errors*

48u/24u inverter Schematic:

*Check: No Errors*

Following the schematics, now we must process the following to symbols!

Symbol of 12u/6u Inverter:

Symbol of 48u/24u Inverter:

Now, to the fun part, we design the layout of the 48/24u Inverter:

Layout of 48u/24u Inverter:

Once the schematic is created, we then Verify->DRC and make sure the layout follows the rules.

Now, Once the layout has passed it’s DRC checks, we then extract the layout and setup for the LVS check from the previously made schematics.

Extracted->LVS of 48u/24u Inverter:

*SUCCESS!*

Once the checks from DRC to LVS satisfies it’s net-list (net-list match!),

We then move forward to the next experiment.

Experiment 2:

The Symbol that was previously created will now be implemented into the given circuit.

Circuit using 48u/24u Symbol:

*Check: No Errors*

Circuit using 12u/6u Simulations:

*Check: No Errors*

Once we have setup for the circuit, we now perform a simulation with varies parameters:

100 fF - 100 pF capacitive load (12u/6u):

100 fF - 100 pF capacitive load (48u/12u):

Through careful analysis, we see that dependent on the size of the capacitor, if the size of the capacitor increases the response time of the signal starts to increase as well.

Experiment 3:

Finally, for the final experiment, we now perform a similar simulation using the Ultrasim application in CADENCE.

Ultrasim 48u/24u Inverter:

Ultrasim 12u/6u Inverter:

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