Lab 3 - ECE 421L 

Authored by David Pinales,

Today's 9/10/21 

Email: pinales@unlv.nevada.edu

Lab description:

In the following lab, I shall be demonstrating my understanding on how to create a layout using a 10-bit DAC w/ a 10k resistor.

Pre Lab:

For the prelab, we finished up the tutorial 1 which was a 10k n-well

Schematic:

Final Product:

Lab 3 Report:

Picking the Length & Width:

It's possible to produce a 10k resistor by using the C5 procedure with the MOSIS parameters file. The n-well utilized in the design has a sheet resistance of around 800 Ohms, according to the file. For example, 3.6 microns is the minimum width of 12 lambda (one lambda is equal to 0.30um). Calculate required length using this minimal value and a desired resistance of 10k using the following equation.

Here’s an example for a better understanding:

From the previous lab’s, here is the 10K resistor layout in which we will be using to create the 10Bit DAC:

Here we have the given 10K resistor w/ the extracted layout presented:

Resistance = 10.21K

- To help verify the results prior to seeing the total resistance, we can measure the N-well by simply doing the following

Keybind “K” -> Measure from point to point (Length & Width) -> Calculate

Now, to form the 10Bit DAC we can use the given schematic as reference:

Schematic of Beginning process:

Symbol of single 10Bit DAC:

Finished view of full 10Bit DAC:

Finally, after combining the finished 10K resistors in series we finally have the following result:

10Bit DAC

After everything was compiled and net-list was a match, the files of this lab are given as a Zip file.

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