Lab 2 - ECE 421L 

Authored by David Pinales,

Today's 8/30/21 

Email: pinales@unlv.nevada.edu

Lab description:

In this lab, I shall be demonstrating my understanding and use of Cadence as well as fully implementing an n-well resistor of 10k with a 10-Bit DAC.

Pre Lab:

For the pre lab, I demonstrated the behavior in a 10 bit ADC to a 10 Bit DAC:

SIMULATION SCHEMATIC:

The simulation output can be seen from the given transient output:

Running the simulation using ADE L:

A 10 bit DAC’s resolution is stated as 2^10=1024

When calculating the LSB, the following equation can be used:

LSB = VDD/2^n = 5/2^10 = 4.88mV

N = the number of bits

VDD = 5V

Output of the given 4.88mV can be seen with the following:

Lab Report:

• The design of a 10-bit DAC using an n-well R of 10k
• The 2R resistor should be implement with two separate 10k resistors in series

The Given schematic as well as symbol is the beginning process for my 10-Bit DAC.

By using the following steps:

- Create 10k series resistors

- Create -> Cellview -> From Cellview

- Save symbol towards schematic

From the given steps, we have the following symbol.

Once the symbol has been created we then move on to creating the schematic for a 10-Bit DAC:

Next, we then create the symbol of the schematic to create the following symbol:

10-BIT DAC:

Now that the symbol has been created, we introduce a quick simulation implementing a Delay in the given schematic:

DELAY:

Discussion of Tolerances in Cadence

Before we simulate the above schematic, we need to change the tolerance options in order to force the simulation.

Force the simulation by doing the following:

• ADE, Simulation -> Options -> Analog

• Set the values as seen below 
• relative tolerance, reltol, of 10% (= 1e-1)   
• voltage absolute tolerance, vabstol, of 100 mV (= 1e-1)  
• current absolute tolerance, iabstol, of 1 mA (= 1e-3)  
• The accuracy of the simulation will, obviously, be degraded 

The output can be seen:

Driving DAC w/a Pulse: 0 -> 5V

Predicted td = 0.7RC = 0.7(10^3)(10^-12) = 70ns

 1 LSB = VDD/2^N = 5/2^1 = 2.5V

time delay is calculated at half of the input which is 2.5/2 = 1.25V

Now, we have the following schematic with my own 10-Bit DAC and implementing it to the given schematic using a 10-Bit ADC:

10-Bit Driving an ADC no load:

Simulation results:

Schematic of DAC to a Ideal ADC w/ a 10k load:

Simulation Results:

output magnitude cut in half, in phase with input

Driving DAC to an Ideal ADC w/ 10p F load:

Simulation Results:

output is delayed and smooth out curves.

Driving DAC an Ideal ADC with a 10k and 10pF in parallel load:

Simulation Results:

output magnitude is cut in half and delayed

Questions: Discuss what happens if the resistance of the switches isn't small compared to R.

-   If the switch's resistance is near to R, it will serve as an additional resistor, resulting in a 3R R voltage divider and a lower output voltage.

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