Project : Register File
EE 421L Digital IC Design

By: David Nakasone – Email: nakasd3@unlv.nevada.edu
Assigned: September 22, 2021
Due: November 17, 2021 / November 24, 2021


Lab description >>>

This project is to design a 32x8 register file (RF). The RF stores 32 8-bit words.
A 5-bit address scheme is used to access the 32 words.
The memory is not bit addressable.
Inputs include: address, ground, power, and read/write.
The next steps require:
    row driver, sensitivity analyzer, pre-chargers, and bit comparators.
When complete, this circuit is intended to operatate as an SRAM unit.

There are 7 major tasks for this lab:

    A) design, layout, and simulate: inverter
    B) design, layout, and simulate: bit cell
    C) design, layout, and simulate: word cell
    D) design, layout, and simulate: word array (32x8)
    E) design, layout, and simulate: and gate, 5 inputs
    F) design, layout, and simulate: decoder, 5x32
    G) design, layout, and simulate: SRAM

Simulations initialize the internal bit cell to a logic 0 value.
Also, simulation durations are kept short, until precharging is availible.

Part A : inverter >>>
The inverter was sized to maintain a stable switching point.
This inverter is used multiple times in the SRAM sub-modules.
Using the C5 process, a 48u standard height allows the design to be efficiently constructed.


[ A1 ]  schematic
s

[ A2 ]  symbol
s

[ A3 ]  verification circuit
s

[ A4 ]  simulation
s

[ A5 ]  DRC
s

[ A6 ]  LVS
s



Part B : bit cell >>>
 The bit cell is accessed by NMOS pass gates that are sized not to overpower to latch.
Subsequent modules are designed to accomodate the stored data.

[ B1 ]  schematic
a

[ B2 ]  symbol
a

[ B3 ]  verification circuit
a

[ B4 ]  simulation, descending into the bit cell to observe the latch:
s

[ B5 ]  DRC, the bit-cell is configured with adventageous linkage points of different metals
d

[ B6 ]  LVS
d


Part C : word cell >>>
The word cell is 8 bit cells. This represents one row of the memory unit.

[ C1 ]  schematic
a

[ C2 ]  symbol
a

[ C3 ]  verification circuit
a

[ C4 ]  simulation, descending into bit<5>, the cells are able to receive and store data
a

[ C5 ]  DRC
a

[ C6 ]  LVS
a


Part D : word array >>>
This array is 32 word cells, completing the 32x8 design.
Included with a proper decoder, the circuit will be able to function as an SRAM.
The future work would include the pre-charger and sensitivity analyzer on this module.

[ D1 ]  schematic
f

[ D2 ]  symbol
f

[ D3 ]  verification circuit
h

[ D4i ]  simulation, the word line for row<0> is on a pulse source

f

[ D4ii ]  simulation, the word line for row<10> is always on
f

[ D4iii ]  simulation, the word line for row<20> is always off
j

[ D5i ]  DRC, top of memory unit
d

[ D5ii ]  DRC, bottom of memory unit
d

[ D5iii ]  DRC success
d

 [ D6 ]  LVS
n


Part E: and5 >>>
Using a 5-input NAND gate and placing the inverter at the output, the AND gate is realized.
This gate will receive the row driver for further applications.

 [ E1i ]  schematic, preparing a NAND gate
f

[ E1ii ]  schematic, AND gate formed
f

[ E2 ]  symbol
d

[ E3 ]  verification circuit
d

[ E4 ]  simulation, the AND gate is only "1" on "11111"
d

[ E5 ]  DRC
f

[ E6 ]  LVS
f


Part F: decoder >>>
Using 31 AND gates, this decoder selects exactly 1 of 31 rows.
Larger designs may benifit from tree decoding and precoding.
The data is addressable up to 1 GHz clock speeds.

[ F1 ]  schematic
d

[ F2 ]  symbol
d

[ F3 ]  verification circuit
d

[ F4 ]  simulation, row<0>, row<15>, and row<31> are properley selected
f

[ F5i ]  DRC, top of decoder
d

[ F5ii ]  DRC, bottom of decoder
d

[ F5iii ]  DRC
d

 [ F6 ]  LVS
d


Part G: SRAM >>>
The SRAM is formed by combining the word array and decoder.
This circuit is capable of storing data in each of the 256 bit cells.

[ G1 ]  schematic
d

[ G2 ]  symbol
d

[ G3 ]  verification circuit
d

[ G4i ]  simulation, row<16> bit<4>
d

[ G4ii ]  simulation, row<31> bit<2>
d

[ G5i ]  DRC, decoder joined to memory unit
d

[ G5ii ]  DRC, inout at bottom of SRAM
d

[ G5iii ]  DRC
d

[ G6 ]  LVS
d



The circuit is ready for periphrial components.
Design files available on request.
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