Lab

[ 1 ] create a pad layout, verify with DRC

[ 2 ] copy a 12x12 array, after making a pin arry and deleting pad layer;
all the pins must be renamed

[ 3 ] ensure the pad frame is free from errors, there are now pins <1:40>

[ 4 ] make the schematic for the pad (just an input/output pin)

[ 5 ] make a symbol of the pad, from the schematic

[ 6 ] use an array to make a schematic of the pad frame symbol

[ 7 ] make a symbol of the pad frame schematic

[ 8 ] make a schematic of the chip

[ 9 ] place the components in a layout and verify with DRC, clean up layout for project

This is the basis for applying components to the actual chip.

Part B : design plan >>>
* each circuit requires its own power supply (pin), but ground is common to all on pin<20>
** connections have a minimum of 2 vias
*** DRC is completed after every connection is made on the chip
**** LVS is confirmed before adding another circuit to the chip

[ B1 ] pad frame
Using tutorial 6, the pad frame is in good working order.
Also, maintaining the 48 um standard cell height ensures accurate and efficient layout.

[ B2 ] layout cell
This cell is the basis for DRC and LVS of the entire chip.
Components are not allowed be placed on the chip until they are individually validated.
[ B2i ] the top-level schematic

[ B2ii ] adding new layouts to the chip

[ B3 ] test cell
This cell is a direct abstraction of the clean chip cell.
A seperate test bench was constructed to ensure that the manufacturer receives the design exactly as specified.
On-chip testing can be simulated here, as if the end user was operating the finished design.
[ B3i ] test cell schematic, components are placed exactly how layout was conducted: