[ 2 ] The brute-force schematic is still correct.
[ 3 ] using multiple instances, schematics should use an array.
[ 4 ] create a symbol of the proper schematic
[ 5 ] apply the schematic symbol to a testing circuit
[ 6 ] simulate to verify the schematic is correct
[ 7 ] layout the 31-stage ring oscillator
[ 8 ] ensure the layout is correct with DRC
[ 9 ] extract and LVS the layout
[ 10 ] simulate the extraction
[ * ] route array as intended with label, but only pins are recognized
[ ** ] apply vdd! in the simulation, bad to include 5 V dc as nesting occurs
[ *** ] noise in circuit will eventually get oscillator going, but use an initial condition
Part B : analyze the CMOS inverters >>>
[ 1 ] ensure the existing CMOS is modeling the inverter correctly
[ 2 ] reference the inverter schematic as a symbol
[ 3 ] apply the symbol of the inverter to a circuit for verification
[ 4 ] the CMOS inverter (not gate) is operating correctly, proceed to further use
[ 5 ] build the 4x inverter by instance
[ 6 ] create a symbol of the 4x inverter
[ 7 ] apply the symbol to a testing circuit (note relationship of capacitive loads)
[ 8 ] simulation confirms correct operation, increasing time constant with increasing capacitance
Part C : gate arrays >>>
[ NOT 1 ] create an array of inverters
[ NOT 2 ] create a symbol of the schematic, inputs/outputs established
[ NOT 3 ] build a test circuit
[ NOT 4 ] simulate and verify results (matches truth table above)
[ AND 1 ] create an array of AND gates "~NAND"
[ AND 2 ] create a symbol of the schematic, inputs/outputs established
[ AND 3 ] build a test circuit
[ AND 4 ] simulate and verify results (matches truth table above)
[ NAND 1 ] create an array of NAND gates
[ NAND 2 ] create a symbol of the schematic, inputs/outputs established
[ NAND 3 ] build a test circuit
[ NAND 4 ] simulate and verify results(matches truth table above)
[ OR 1 ] create an array of OR gates "~NOR"
[ OR 2 ] create a symbol of the schematic, inputs/outputs established
[ OR 3 ] build a test circuit
[ NOR 1 ] create an array of NOR gates
[ NOR 2 ] create a symbol of the schematic, inputs/outputs established
[ NOR 3 ] build a test circuit
[ NOR 4 ] simulate and verify results (matches truth table above)
Part D: mux and demux >>>
[ mux 1 ] theory behind provided MUX
The DEMUX is a decoder and reverses the MUX. The original input could be realized by the DEMUX.
Reverse the pins and DEMUXing is achieved.
[ mux 2 ] create a test circuit to simulate the provided MUX
[ mux 3 ] the simulation is valid: Z = A when S = 1 ; Z = B when S = 0
[ mux_i 1 ] apply an inverter to the original design
[ mux_i 2 ] update the 2:1 MUX symbol
[ mux_i 3 ] build a test circuit
[ mux_i 4 ] verify the results, the circuit is valid: Z = A when S = 1 ; Z = B when S = 0
[ mux bus 1] establish the schematic
[ mux bus 2] derive the symbol
[ mux bus 3] prepare the testing circuit
[ mux bus 4] confirm the simulation A = 0000_0000 , B = 1111_1111
if S = 1111_1111, Z = A
if S = 0000_0000, Z = B
Part E: the 8-bit full adder >>>
[ fa 1 ] expand the full adder of lab 6, the schematic allows 8-bits in cascade
* this full adder has been previously validated and is in good working order
[ fa 2 ] create a symbol of the schematic
[ fa 3 ] make a testing circuit
[ fa 4 ] ensure correct operation before proceeding to layout
[ fa 5 start ] cin is the only non-array input pin
[ fa 5 transition ] internal transitions place input an output pins, but carry Cout-->cin
[ fa 5 stop ] the only carryout pin is at the end of the adder. It can also be used to extend the adder
[ fa 5 ] DRC the full adder to verify layout
[ fa 6 ] extract the layout
[ fa 7 ] check the layout with LVS
[ fa 8 ] apply the extraction to the simulation to verify results
Files correctly named:
Design files availible on request