Lab

Lab 6 : Digital Integrated Circuit Design
EE 421L Digital IC Design

By: David Nakasone – Email: nakasd3@unlv.nevada.edu
Assigned: October 6, 2021
Due: October 20, 2021

Lab description >>>

    The building blocks of digital circuits are logic gates.
This lab will design basic gates, combining them to build a full-adder.
Design, layout, and simulation continue to fundamental and critical.
As these designs become more complex, the best technique is to build in managable sections.
Dividing the work ensures smaller components can be properly made and placed into the larger design. These labs are cummulative, and emphasize real-world techniques.
Cadence is a successful program, but the designer must be aware of all the problem areas.

There are four major tasks for this lab:

    A) Complete and document “tutorial 4”
    B) Design, layout, and simulate: the 2-input NAND gate
    C) Design, layout, and simulate: the 2-input XOR gate
    D) Design, layout, and simulate: the full-adder

Part A : tutorial 4 >>>

[ 1 ] build NAND gate schematic

[ 2 ] create the NAND gate symbol

[ 3 ] build the simulation schematic

[ 4 ] simulate the NAND gate schematic

[ 5 ] layout and DRC the NAND gate

[ 6 ] extract the layout

[ 7 ] validate the layout with LVS

[ 8 ] simulate the extraction, compare to schematic

Part B : the NAND gate >>>

[ 1_NAND ] make a gate schematic using 6u/0.6u devices

[ 2_NAND ] make a symbol of the gate

[ 3_NAND ] verify correct operation of the schematic with a testing circuit

[ 4_NAND ] the results are consitent with the truth table, proceed to layout

[ 5_NAND ] layout the NAND gate and ensure DRC

[ 6_NAND ] extract the layout

[ 7_NAND ] verify with LVS

[ 8_NAND ] simulate the extraction, results must be same as schematic simulation

Part C : the XOR gate >>>

[ 1_XOR ] make a gate schematic using 6u/0.6u devices

[ 2_XOR ] make a symbol of the gate

[ 3_XOR ] verify correct operation of the schematic with a testing circuit

[ 4_XOR ] the results are consitent with the truth table, proceed to layout

[ 5_XOR ] layout the XOR gate and ensure DRC

[ 6_XOR ] extract the layout

[ 7_XOR ] verify with LVS

[ 8_XOR ] simulate the extraction, results must be same as schematic simulation

Part D : the full adder

[ 1_FA ] make a schematic using instances

[ 2_FA ] make a symbol of the full adder

[ 3_FA ] verify correct operation of the schematic with a testing circuit

[ 4_FA ] the results are consitent with the truth table, proceed to layout

[ 5_FA ] layout the full adder and ensure DRC

[ 6_FA ] extract the layout

[ 7_FA ] verify with LVS

[ 8_FA ] simulate the extraction, results must be same as schematic simulation

files correctly named:

design files availible on request

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