Lab 3: Layout 10-bit DAC
EE 421L Digital IC Design
By: David Nakasone – Email: nakasd3@unlv.nevada.edu
Assigned: September 8, 2021
Due: September 15, 2021
Lab description >>>
This lab focuses on the 10-bit DAC desinged and
simulated in Lab2. Using the guidance of "tutorial 1", the student will
be able to select the proper components and layers for the layout of
this circuit. With proper technique, a successful "Layout vs Schematic"
or LVS can be achieved. Once successful, the circuit is ready for
further implementaiton.
A) Complete and document “tutorial 1”{finish, and back up work}
B) Layout the DAC
Part A : tutorial >>>
[ 1 ] make the schematic general purpose with pins
[ 2 ] make the schematic general purpose by creating a symbol
[ 3 ] simulate the symbol to verify it works
[ 4 ] ensure results are that of a 1/2 voltage divider
[ 5 ] layout the resistor n-well, use DRC as much as possible
[ 6 ] install the ntaps
[ 7 ] apply DRC before extraction
[ 8 ] check the resistance
[ 9 ] use the resistor as a module to make the voltage divider
[ 10 ] successful LVS ensures layout will work according to the schematic
Part B : layout>>>
[ 1 ] resistor selection
[ 2 ] using the 10k n-well, create a ladder module (verify by DRC and LVS)
[ 3 ] build the DAC layout to match the verified DAC symbol/schematic
an additional resistor and ground pin must be included:
[ 4 ] confirm the design complies with rules using verify->DRC
[ 5 ] layout vs schematic, to confirm this design, after successful extraction
[ 6 ] review the output of LVS
[ 7 ] link to lab3 design files: here