Lab 3: Layout 10-bit DAC
EE 421L Digital IC Design

By: David Nakasone – Email: nakasd3@unlv.nevada.edu
Assigned:
September 8, 2021
Due: September 15, 2021




Lab description >>>

    This lab focuses on the 10-bit DAC desinged and simulated in Lab2. Using the guidance of "tutorial 1", the student will be able to select the proper components and layers for the layout of this circuit. With proper technique, a successful "Layout vs Schematic" or LVS can be achieved. Once successful, the circuit is ready for further implementaiton.

    A) Complete and document “tutorial 1”{finish, and back up work}
    B) Layout the DAC




Part A : tutorial >>>

[ 1 ]  make the schematic general purpose with pins
schematic

[ 2 ]  make the schematic general purpose by creating a symbol
symbol

[ 3 ] simulate the symbol to verify it works
sim sym

[ 4 ]  ensure results are that of a 1/2 voltage divider
results

[ 5 ]  layout the resistor n-well, use DRC as much as possible
resistor

[ 6 ]  install the ntaps
ntap

[ 7 ]  apply DRC before extraction
check layout

[ 8 ]  check the resistance
10.18k

[ 9 ]  use the resistor as a module to make the voltage divider
R_div

[ 10 ]  successful LVS ensures layout will work according to the schematic
LVS good


Part B : layout>>>

[ 1 ]  resistor selection
r10k

[ 2 ]  using the 10k n-well, create a ladder module (verify by DRC and LVS)
DRC ladder module

LVS ladder

[ 3 ]  build the DAC layout to match the verified DAC symbol/schematic
             an additional resistor and ground pin must be included:
add R

[ 4 ]  confirm the design complies with rules using verify->DRC
drc


[ 5 ]  layout vs schematic, to confirm this design, after successful extraction
lvs ran

[ 6 ]  review the output of LVS
LVS output

[ 7 ]  link to lab3 design files:  here

                 



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