Lab 4 - EE 421L
Authored
by Charlene Drake
Email: drakec2@unlv.nevada.edu
September 22, 2021
Prelab
To
start off, we needed to complete Tutorial 2, where we learned how to
design the schematic and layout for a NMOS and PMOS transistor.
NMOS:
PMOS:
With
our schematics and layouts complete we were able to extract from the
layout and compare the netlist to that of the schematic with an LVS
check.
Once the netlists matched, we could simulate the schematics.
NMOS:
PMOS:
Lab Procedures
A
schematic for simulating ID v. VDS of an NMOS device for VGS varying
from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV
steps. Use a 6u/600n width-to-length ratio:
A
schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV
where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n
width-to-length ratio:
A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio:
A
schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV
where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n
width-to-length ratio:
Layout of a 6u/0.6u NMOS Device connected to Probe Pads:
The
first thing we needed to do for our design was to create a schematic
for the probe pad with an input pin and then create the symbol.
From there we needed to create the layout.
Next, we needed to design the NMOS schematic which had a probe pad connect at each terminal.
From there, we were able to create the layout of the NMOS with the probe pads.
After extracting we were to have a clean DRC and LVS.
Layout of a 12u/0.6u PMOS Device connected to Probe Pads:
To create the schematic for the PMOS device we use the probe pads we created for the NMOS design. A probe pad was connected to each terminal.
From there we were created the layout of the PMOS with the probe pads.
After extracting we were to have a clean DRC and LVS.
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