Lab 2 - EE 421L 

Authored by Charlene Drake,

Email: drakec2@unlv.nevada.edu

September 08, 2021

Prelab

1.)

For this lab, we started out by extracting and downloaded the provided lab2.zip. We then needed to add the line "DEFINE lab2 $HOME/CMOSedu/lab2" to our cds.lib.

Once we had the file open on Cadence, we were able to access the sim_ideal_ADC_DAC schematic and run the simulation.

From loading the save state were given the following simulation.

2.) In order to demonstrate my understanding of how ADC and DAC, I changed amplitutde of the input to 5mV. As you can see, the number of "steps" in the output has decreased. This is due to the smaller input voltage since the height of the steps is calculated by the least significant bit in the DAC.

3.) From the prelab we were given the equation 1LSB = VDD/2^N where VDD is the input voltage and N is the bit width. Since we are working with a 10-bit output, the N for our equation would be 10. Then, from our original schematic and the simulation we know that VDD = 5V. We can then calculate for the least significant bit.

1LSB = 5V/2^10 = 4.88mV

With this information we can change the amplitutde and DC offset to 2.44mV and we are given the following results.

As you can see, the LSB is the smallest amount of change in the input before there is a change in the output and simulation agrees with our calculation of the LSB.

Lab Procedures

The first thing we needed to do in this lab was to design a 10-bit DAC using a n-well R of 10K.

Once our n-well was created we designed the 10-bit DAC by connecting 10 of the n-well signals. With n-well B0, the bottom bit is connected to a 10k resistor whereas with every bottom bit after that, all the way up to n-well B9's, the bottom bit is fed into the output of the previousn-well.

Next we were to verify and test out our 10-bit DAC by calculating the R Total and the time delay.

For our schematic we were to ground every input besides B9 and then combine all of the resistors in parallel which left us with 10k, as seen in the hand calculations. With that 10k we were able to calculate for the time delay since td = 0.7RC.

As you can see, our hand calculations matched up with the simulation and the time delay was in fact 70ns.

Next we needed to make a copy of the sim_Ideal_ADC_DAC file and replace the DAC with our design.

This was the simulation after using the 10-bit DAC that I designed.

10k Load:

10pF Load:

When the DAC drives a 10pF load the output is not longer a pulse, but it does lag.

RC Load:

When the DAC drives an RC load, again the output voltage lags and is no longer a pulse. It is also about half of the input voltage.

If the resistance of the switches are not small compared to R then the equivalent resistance of the DAC would no longer be R. R would need to be added to each series resistance making the equivalent resistance higher which also leads to a higher output resistancce.

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