Lab 2- EE 421L Fall 2020
Authored by: Nathan Pina
Email: pinan1@unlv.nevada.edu
Due Date: 9/9/20
Lab
description:
Design of a 10-bit digital-to-analog converter (DAC)
Pre-Lab:
In your lab report:
1) provide narrative of the steps seen above,
2) provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC,
3)
explain how you determine the least significant bit (LSB, the minumum
voltage change on the ADC's input to see a change in the digital code
B[9:0]) of the converter. Use simulations to support your understanding.
The
first part of the pre-lab involved downloading the Lab 2 zip folder and
unzipping it into the CMOSedu design directory. Once this was done, I
made sure to define the directory in the cds.lib so that it appears in
the library manager.
I opened the schematic view and proceeded to simulate the circuit at the default paramters (2.5V amplitude).
To
further demonstrate my understanding of the ADC and DAC, I modified the
cirucit by changing the amplitude of the input to 5mV. From the
simulation, with a much lower input voltage the amount of steps the
output takes is much lower when compared to the default 5V. The
height of these steps is calculated by the DAC though the least
signficant bit (LSB). The LSB is the minimum change that the input can
have before a change in the output can be seen and is determined with
the following formula: VDD/2^n.
In this case, VDD will be 5V while n is equal to 10 (based on the fact
that this design is 10 bits). When calculated the LSB will be
approximately 4.88mV, matching closely to the simulation.
Main Lab Work:
The
main portion of this lab will involve designing a 10-bit DAC using an
n-well R of 10k. Then I will take this DAC and implement it in a
seperate design in conjuction with a ADC under various load conditions.
The topology of the cirucit will be based on Fig. 30.14 seen below.
1.) Output Resistance of DAC
The
resistance of the DAC can be determined by the combination of parallel
and series resistors. Below is a diagram of the resistor combinations
starting at bit 0, and will continue upwards until the last bit. In the
case of this design it will stop at bit 9 and ultimately result in an
output of R or 10k.
2.) Creation of DAC symbol
Instead
of creating a brand new symbol for my design, I modified the
preexisting schematic (Ideal_10-bit_DAC) by creating a copy of it. This
can be done by right clicking the existing cell and selecting
"Copy". Rename the file to "My_Ideal_10-bit_DAC" and checking the box
labeled "Copy All Views" to copy not only the schematic but the sybmol
and all other realted files as well.
From
here, you can start to modify the schematic to your liking and delete
the unnecessary portions of the design like Vrefp and Vrefm. Below is
my modified DAC design as well as the DAC being replaced in the main
simulation test schematic.
3.) Delay of DAC driving a 10pF load
The time delay of the DAC under a capacitive load of 10pF can be hand calculated using the formula td = 0.7RC,
where R is the equivalent resistance of the DAC and C is the
capacitance of the load. Plugging the values into the equation results
in a theoretical time delay of about 70ns.
Running
the simulation, we can see that capacitor begins charging at 0.5us or
500ns. At about 570ns the output reaches 1.25V, which is half the max
voltage of 2.5V. The difference between these two times is 70ns, equal
to the hand calculated results of the time delay formula.
4.) Main Circuit Simulations Under Various Loads
The
last portion of this lab involves testing the ADC/DAC circuit under
various load conditions which are as follows: no load, 10pF load only,
10k load only, and 10pf + 10k load.
No load:
Under
no load conditions, the digital signal will follow the amplitude of the
analog signal, similar to that of the ideal DAC in the prelab.
10pF Capacitive Load:
Under
a 10pF capacitive load, the previous calculated 70ns delay starts to
take affect on the output. The output voltage swing has also changed
with it varying from ~0.98V to 4.1V instead of the input swing of 0V to
5V.
10k Resistive Load:
Under
a 10k resistive load, the ouput will be cut in half as the load
resistance and equivalent resistance of the DAC will form a voltage
divider with two 10k resistors.
10k/10pF Combination Load:
Under
a 10k resistive load and 10pF capacitive load, the output will be a
combination of the previous tests. The output voltage will be halved
due to the voltage divider while also being delayed and having a lower
voltage swing because of the capacitor.
5.) Real Cirucit Question
In
a real circuit the switches seen above (the outputs of the ADC) are
implemented with transistors (MOSFETs). Discuss what happens if the
resistance of the switches isn't small compared to R.
If the
resistances of the switches were not small compared to R, the
equivalent resistance of the DAC would be changed. Since the
resistances of each bit would be higher, the resistance of the DAC
would also be higher. This increase in resistance would cause a bigger
voltage drop between the ADC and DAC and result in a lower output
voltage.
Lab Backup
After
I completed this lab, I made sure to back up all files (schematics,
simulations, screenshots etc.) into a zip file and upload to my Google
Drive.
