Lab Project - EE 421L 

Authored by Michael Nguyen

Email: nguyem9@unlv.nevada.edu

11/18/2020

Lab description:

Project (not a group effort, each student will turn in their own project) – design, layout, and simulate a digital receiver circuit that accepts a 

high-speed digital input signal D and Di (a differential pair connected to your circuit from, for example, a twisted pair of wires such as in an 

Ethernet cable). D and Di are complements so, for example, if D is 5V then Di is 0V and output = 1. Another example, when D is 1V and Di is 2V

then output = 0. At high-speeds and long distances the voltages received aren't full digital logic levels (i.e., 5V and 0V), hence the need to design, 

and use, a high-speed digital recevier circuit. Ideally, when D > Di the receiver outputs a 1. When D < Di the receiver outputs a 0. Base your 

design on the topology seen in Fig. 18.23. Try to design for high-speed and low-power. Characterize your design (in sims) and the trade-offs. 

For example, show that you get higher-speed if you use more energy (burn more power). See if you can get, in this 500 nm process, 250 Mbits/s

(a bit width of 4 ns) with an input voltage difference of, for example, 250 mV (with D and Di swinging back and forth between 2.75V and 3V, 

for one of many examples, your circuit outputs the correspondingly correct values). Note that while Fig. 18.23 shows one inverter on the output 

you may find, for example, that two inverters work better (at the cost of power). Use a table to summarize your design's performance.

Design:

 

Transistor view                                                                                Symbol

                                                       

 

Two 12u/6u inverters from lab 5                                                                                                     Symbol

                          

                 

Different Clock Frequency
Clock frequency: 125MHz
8ns period
Clock frequency: 250MHz
4ns period
Clock frequency: 500MHz
2ns period
Clock frequency: 1GHz
1ns period
As the clock frequency gets faster the logic wave accuracy does start to decrease, but at 500MHz it does reach full logic level
but the logic wave falls somewhat apart. At 1GHz the receiever just could not take it. On that note the sweet spot of 4ns period works.
                 
 Various VDD                                                       
VDD = 5
VDD = 4
VDD = 3
VDD = 2
VDD = 1
At VDD = 4V the logic wave is now from 0 to 4 instead of 0 to 5, at VDD ≤  3V the logic wave starts to fall apart..
                           
Speed Vs Power                
125 MHz
250 MHz
500 MHz
1GHz
As frequency increases the power dissipated goes up. The trade off is that we have speed at the cost of using up more power
                             
Different Input Voltages and Voltage Differences
Input: 5 and 0
Difference: 5
Input: 5 and 2.5
Difference: 2.5
Input: 2.5 and 1.5
Difference: 1
Input: 1.5 and 1
Difference: 0.5
Input: 1 and 0.9
Difference: 0.1
Voltage differences do affect the output but not significantly, but at 0.1 volt difference the output starts to falls apart; any smaller it
would not function correctly.
               
Temperature Effects

 
Increasing L vs. Power                
L = 1.2u
L = 2.4u
L = 4.8u
L = 5.6u
As the L increases the less current the circuit draws, so therefore power dissipation goes down.         
   
L=1.2u vs Varying Speed                     
125MHz
250MHz
500MHz
1GHz
                                           
 L=2.4u vs Varying Speed                        
125MHz
250MHz
500MHz
1GHz
               
                 
L = 4.8u vs Varying Frequency
125MHz
250MHz
500MHz
1GHz
     
   
L = 5.6u vs Varying Frequency
125MHz
250MHz
500MHz
1GHz
According to all these test it shows that increasing the L is good for reducing power, but in the process speed suffers for it.
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Layout design



     

Projectzip