Lab 7 - EE 421L 

Name: Cole Moreno

Email: morenc6@unlv.nevada.edu

Date: November 10, 2020

    

    

Pre-Lab

   

First I followed the directions of Tutorial 5 and created the 31 stage Oscillator Ring Schematic.

   

   

Then, I laid out the schematic and checked that it passed DRC and LVS.
   

   

     

   

Next, I was asked to simulate the 31 stage ring oscillator with a symbol view.

   

   

   

   

Next going through the steps of Tutorial 5, I was asked to change the display net to the extracted file which is shown below.

   

   

   

Lab

   

For the lab, the first thing I did was to design a 4bit inverter schematic using the techniques from the prelab. I then created a simulation schematic with different capacitance loads to see how the different capacitance values affected the simulation results.

 

     

   

     

Next I did the same thing for the NAND, NOR, AND, inverter, and OR gates. For each of these gates I created an 8bit input/output array and created a simulation schematic, hooked up a couple of the outputs to capacitance loads and observed the results.

   

NAND

  

   

     

   

 

NOR

    

         

   

   

       

   

   
   

AND

   

       

   

     
   

INVERTER

   

         

     

     

   

OR

   
         
   

     

Next I created the 2-to-1 DEMUX/MUX schematic and symbol. I created the one instance MUX and the array MUX as well (for 8bit).

   

         

     
   

         

   

   

After creating the schematic and the symbol, I simulated the MUX and the DEMUX functionality of the symbol view. I simulated for both the single instance and the array instance (8bit).

   

MUX

    

       

      

   

       

   

   

DEMUX

    

         

     
     

   

   
Next, I created the schematic of the full adder from Fig 12.20 using 6u/0.6u devices.
   

   
Then I created the layout and verified the design with DRC and LVS.
   

   
         
   
Next, I needed to create the schematic, symbol for the 8bit full adder. I also created a simulation schematic and simmed to show that the full adder funcitoned properly.
   
         
   

   

   
To simulate the operation of the full adder I used the two numbers: A = 00000011 and B = 00001100. The result should be S = 00001111.
   

   
The next step was to layout the full 8bit full adder and check that the layout followed DRC and matched the schematic with LVS.
   

   

   
         
   
Finally I backed up my CMOS files and my pictures into a zipped file and saved them to my google drive folder dedicated to backups.
      

   

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