Lab 7 - EE 421L
Pre-Lab
First I followed the directions of Tutorial 5 and created the 31 stage Oscillator Ring Schematic.
Then, I laid out the schematic and checked that it passed DRC and LVS.
Next, I was asked to simulate the 31 stage ring oscillator with a symbol view.
Next going through the steps of Tutorial 5, I was asked to change the display net to the extracted file which is shown below.
Lab
For the lab, the first thing I did was to design a 4bit inverter schematic using the techniques from the prelab. I then created a simulation schematic with different capacitance loads to see how the different capacitance values affected the simulation results.
Next I did the same thing for the NAND, NOR, AND, inverter, and OR gates. For each of these gates I created an 8bit input/output array and created a simulation schematic, hooked up a couple of the outputs to capacitance loads and observed the results.
NAND
NOR
AND
INVERTER
OR
Next I created the 2-to-1 DEMUX/MUX schematic and symbol. I created the one instance MUX and the array MUX as well (for 8bit).
After creating the schematic and the symbol, I simulated the MUX and the DEMUX functionality of the symbol view. I simulated for both the single instance and the array instance (8bit).
MUX
DEMUX