Lab 6 - EE 421L 

Name: Cole Moreno

Email: morenc6@unlv.nevada.edu

Date:  October 20, 2020

Pre Lab

For the prelab, I went through Tutorial 4, which went through designing and layout of a nand gate in CMOS. 

First, I created the schematic for the nand2 gate.

Next, I created the symbol for the nand gate.

Next, the tutorial went through simulation using the nand gate, to show the outputs for any combination of inputs (A and B).
   

After getting the correct results from the simulation, I was instructed to create the layout and verify that it passes DRC and LVS tests.

Lastly, I was asked to include the MOSFETS in the LVS check, and verify that the layout still passes LVS with this added parameter.

Lab

For the lab, we were instructed to create the nand, xor gate schematics first, then the symbols for each schematic respectively. From the prelab, the nand gate was already designed.

NAND

   
XOR

Next, was to design the layout for each the nand and the xor gates, make sure each passes DRC and LVS against the original schematics.

NAND

XOR

The next step in the lab, was to simulate the xor, nand, and inverter gates in a simulation schematic, using all combinations of inputs A and B. The following results were recorded, after creating the schematic below.

The glitches, seen in the simulation results, namely on the AxorB and AnandB results at time 200 ns, can be attributed to the shift of the A input from 0 to 1. When this instantaneous shift happens, the XOR and NAND gates have somewhat a delay on the output, so the instantaneous shift causes the outputs of the NAND and XOR gates to be pulled down slightly, before the signal propogates and the time delay has been cleared. 

Creating each of these gates, and throwing them into simulation, a couple of things stood out to me. Firstly, when I was running through the simulations on the above schematic, I originally forgot to put the VDD node in the schematic, and when I went to go see the simulation results, nothing had changed. All the results were 0 throughout the window of the simulation. After putting in the VDD node, only then did the simulations come out correctly as expected.

Next in the lab was to create the schematic, symbol, and layout of the full adder gate, also to backcheck that the schematic was drafted correctly, I was asked to simulate the symbol of the full adder and to take note of the results. Then the next and final step was to make sure that the layout passed DRC and LVS against the schematic.

Next after creating the symbol, was to create the simulation schematic, and simulate to compare to the expected results of the full adder gate.
   

   

   
     

After verifying that the simulation results matched the table attached below, the next step was to create the layout view and make sure that it passes DRC and LVS against the original schematic.
     

     

     
         
   
Finally, the last step was to go through the back up process of lab 6. I downloaded all the contents of lab 6 from Cadence, and saved the images used in this report in the file as well. I then saved the zip file in my google drive account.
   

   
         
   
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