Lab 5 - EE 421L 

Name: Cole Moreno

Email: mornc6@unlv.nevada.edu

Date: September 30, 2020
     
Pre Lab

For the prelab, I went through Tutorial 3 on the website. First, the tutorial had me create an inverter schematic.

Next, the tutorial went through creating the layout view for this schematic. The objective was to use DRC and LVS to ensure that the layout and schematic matched and that there were no design errors in the layout view.

After checking those two modalities on the layout view, we created a symbol for the inverter using the original schematic and drew it in a new schematic to ensure that there are no errors in the schematic.

Lastly, we were asked to ensure that the extracted view would yield the same results  as the schematic with the symbol in it.

Lab

The first task to complete in the lab was to create two schematics, layouts, and symbols with the following dimensions for both a 12u/6u and a 48u/24u inverter.

12u/6u Inverter

48u/24u Inverter

After creating the layout for both devices, I used DRC and LVS to check that there were no design errors in either layout, and that each layout matched the respective schematic drawing.

12u/6u

48u/24u

After ensuring that both DRC and LVS passed without any errors for both layouts I zipped the layouts here

The next step in the lab was to create a new schematic to simulate both inverters against a varying load to observe what the results were from the schematic.

12u/6u

To get the following results, the set up for the ADE can be found below. I set up a transient analysis that runs for 25ns and plots the in and out from the schematic. I also set up the parametric analysis for the various capacitive loads to output all results onto one graph rather than have everyting on multiple graphs.

From the results, one can make a couple of observations. First, is the difference in the resulting graphs from the increased capacitence seen in the schematic. The smallest capacitance value (100 fF or the dark blue graph line) yields the most accurate result following the input. The 100fF capacitive load almost mirrors the negation of the input signal. As the capacitance of the load increases, the less accurate the results become.

Next, we were asked to run the same simulation but rather than using spectre we used UltraSim to get a faster yet less accurate result from Cadence simulation.

48u/24u

As expected, since there are multiple fingers working in this schematic, for the same capacitive loads, the results are more accurate thant eh 12u/6u schematic.This can be attributed to the fact that a wider inverter can handle capacitive loads better.

Finally, I backed up my lab, and all my photos into my back up folder in Google Drive

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