Lab 4 - EE 421L
Name: Cole Moreno
Email: morenc6@unlv.nevada.edu
Date: September 22, 2020
Pre-lab
For
the prelab, I was instructed to create schematics for NMOS and PMOS,
simulate to check that the designs were correctly implemented, and
layout each device respectively. Within the layout, I was instructed to
DRC and LVS the drawings to check that no design rules were violated,
and that the layout matched the schematic.
Going through Tutorial 2, I configured the NMOS and PMOS schematics.
![](3%20PMOS%20Schematic.JPG)
After
creating both the schematics, I ran the simulations for each of the
marked nodes (D for the NMOS and S for the PMOS) ot see that the
original schematic was created correctly. The simulations are for NMOS and PMOS respectively.
![](2%20NMOS%20Simulation.JPG)
![](4%20PMOS%20Simulation.JPG)
Following the tutorial, the next step was to create the layout for both the NMOS and the PMOS.
![](6%20PMOS%20Layout.JPG)
The final step was to show that the two layouts followed the DRC and LVS guidelines.
Lab
In
the lab, I was instructed to revise the original schematic of the PMOS
and NMOS to include probe pads, which I was able to obtain from the
lab4.zip.
![](7%20NMOS%20Schematic.JPG)
![](9%20PMOS%20Schematic.JPG)
After
creating the revised symbols using the schematics from above, I began
running the simulated tests that were asked in the lab.
![](10%20PMOS%20Symbol.JPG)
A
schematic for simulating ID v. VDS of an NMOS device for VGS varying
from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1mV steps.
Use a 6u/600n width-to-length ratio.
![](11%20Simulation%201%20Schematic.JPG)
![](12%20Simulation%201%20Simulation%20Results.JPG)
A
schematic for simulating ID v. VGS of an NMOS device for VDS = 100mV
where VGS varies from 0 to 2 V in 1mV steps. Again use a 6u/600n
width-to-length ratio.
![](13%20Simulation%202%20Schematic.JPG)
To get the results for this simulation I had to make a couple of changes to the simulation analysis. Under the DC analysis I changed the component name to /V0, the Parameter Name to dc and set the stop time to 2.
![](15%20Simulation%202%20Changes.JPG)
![](14%20Simulation%202%20Simulation%20Results.JPG)
A
schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device
for VSG (note VGS) varying from 0 to 5 V in 1 V steps while VSD varies
from 0 to 5 V in 1mV steps. Use a 12u/600n width-to-length ratio.
![](16%20Simulation%203%20Schematic.JPG)
![](17%20Simulation%203%20Simulation%20Results.JPG)
A
schematic for simulating ID v. VSG of a PMOS device for VSD = 100mV
where VSG varies from 0 to 2 V in 1mV steps. Again, use a 12u/600n
width-to-length ratio.
![](18%20Simulation%204%20Schematic.JPG)
To get the results of this simulation I had to make the following changes, I changed the component name under DC analysis to /V0 the parameter name to dc, and I set the stop time to 2.
![](19%20Simulation%204%20Changes.JPG)
![](20%20Simulation%204%20Simulation%20Results.JPG)
The next task in the lab, was to layout a 6u/0.6u NMOS device and connect all four terminals to probe pads.
![](25%20NMOS%20Layout%20Schematic.JPG)
![](26%20NMOS%20Layout%20Schematic%20Zoomed.JPG)
Next, I had to ensure that the layout followed the DRC and LVS guidelines.
![](28%20NMOS%20Layout%20LVS.JPG)
Next, I was tasked to layout a 12u/0.6u PMOS device and connect all 4 terminals to probe pads.
![](21%20PMOS%20Layout.JPG)
![](22%20PMOS%20Layout%20Zoomed.JPG)
Next, I needed to show that the PMOS layout followed the DRC and LVS guidelines.
![](23%20PMOS%20Layout%20DRC.JPG)
Finally, I had to back up all my lab work and photos.
![](Lab%204%20Backup.JPG)
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