Lab 4 - EE 421L 

Name: Cole Moreno

Email: morenc6@unlv.nevada.edu

Date: September 22, 2020

  

Pre-lab

   

For the prelab, I was instructed to create schematics for NMOS and PMOS, simulate to check that the designs were correctly implemented, and layout each device respectively. Within the layout, I was instructed to DRC and LVS the drawings to check that no design rules were violated, and that the layout matched the schematic.

   

Going through Tutorial 2, I configured the NMOS and PMOS schematics.

   

   

     

After creating both the schematics, I ran the simulations for each of the marked nodes (D for the NMOS and S for the PMOS) ot see that the original schematic was created correctly. The simulations are for NMOS and PMOS respectively.

   


   

   

Following the tutorial, the next step was to create the layout for both the NMOS and the PMOS. 

   

   

   

   

The final step was to show that the two layouts followed the DRC and LVS guidelines.

   

Lab

   

In the lab, I was instructed to revise the original schematic of the PMOS and NMOS to include probe pads, which I was able to obtain from the lab4.zip.
   

   

   

After creating the revised symbols using the schematics from above, I began running the simulated tests that were asked in the lab.

     

     

   

A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1mV steps. Use a 6u/600n width-to-length ratio.

   

    


   
A schematic for simulating ID v. VGS of an NMOS device for VDS = 100mV where VGS varies from 0 to 2 V in 1mV steps. Again use a 6u/600n width-to-length ratio.

   

   

To get the results for this simulation I had to make a couple of changes to the simulation analysis. Under the DC analysis I changed the component name to /V0, the Parameter Name to dc and set the stop time to 2.
   

   

   

A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (note VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1mV steps. Use a 12u/600n width-to-length ratio.

   

   

   

A schematic for simulating ID v. VSG of a PMOS device for VSD = 100mV where VSG varies from 0 to 2 V in 1mV steps. Again, use a 12u/600n width-to-length ratio.

   

   

To get the results of this simulation I had to make the following changes, I changed the component name under DC analysis to /V0 the parameter name to dc, and I set the stop time to 2.

   

   

   

The next task in the lab, was to layout a 6u/0.6u NMOS device and connect all four terminals to probe pads.
   

   

   

Next, I had to ensure that the layout followed the DRC and LVS guidelines.

   

     

   

Next, I was tasked to layout a 12u/0.6u PMOS device and connect all 4 terminals to probe pads.

   

   

     

Next, I needed to show that the PMOS layout followed the DRC and LVS guidelines.

   

   

   

Finally, I had to back up all my lab work and photos.

   

          

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