Lab 3 - EE 421L 

Author: Cole Moreno
Date: September 15, 2020

Email: morenc6@unlv.nevada.edu 

Pre Lab

In the prelab, I was asked to finish Tutorial 1, by designing a voltage divider, and running it through LVS. 

First, the resistor value that I was able to get from the extracted layout view was 10.21kΩ.

Next, the prelab required me to finish the voltage divider, and run it through LVS verification to make sure the schematic and the layout matched.

Lab

First, I will be going over how I was able to get the 10.21k Ω. I used the following equation to calculate the length. The width of the resistor is set to 3.6µm, and using the AMI 0.60u C5N (3M, 2P, high-res) technology library the sheet resistance is 800Ω, and we wanted the resistor value to be 10kΩ. 

To be safe, I used 56.1µm for the length of the resistor in the layout view. 

In the lab, one of the objectives was to use the schematic from the 10 bit DAC and compare it to a layout version using LVS to ensure that the net lists match.

To create the layout of the DAC, I instantiated a layout resistor from the prelab. I then had the edit angle set to orthoganol to force the x-position to stay the same, but at the same time, allow me to change the y position. I then, used the metal1 layer to create the pins, and the wires that connect each of the components of the voltage divider, and each of the corresponding voltage dividers together. I needed 31 resitors to create the 10 bit DAC in the layout view. I labeled the pins B9 - B0 and Vout.

Next, I used DRC and LVS to backcheck that there were no errors in the design layout, or mismatches between the 10 bit DAC schematic and the layout versions.

I set the LVS to compare the schematic from the 10 bit DAC and the layout that I just created.

Finally, to back up all important lab information, I did the same thing as the previous two labs.