Lab 2 - EE 421L
I followed the steps provided by the tutorial for the prelab 2. After downloading the zip file, unzipping the file into the directory, and uploading its contents into MobaXTerm I added the code DEFINE lab2 $Home/CMOSedu1/lab2 to the cds.lib file. After opening up Cadence and using the Library Manager to get to the correct schematic (lab2 > sim_Ideal_ADC_DAC > schematic) I launched the ADE.
I loaded the state from the cell view that was set to run a transient analysis and plot the values of Vin and Vout over the period of analysis.,
To demonstrate my knowledge on the DAC and ADC converters, I changed the offset of the input voltage to 500mV rather than 2.5 V, since the offset voltage change, there is not as much of a deviation in the amplitude of the input signal, which affects the output signal since the DAC outputs 0 V when the input voltage is negative. Also there is not as many steps in the output voltage when the input voltage is decreased.
To finish up the prelab, I backed up my lab work to my desktop.
Next, I used the voltage divider symbol to create the DAC Schematic. To do this, I stacked 10 voltage divider symbols, connecting the bottom of one to the out of another. Once the schematic was created I then created another cellview that stored the DAC symbol.
I needed to test the newly created DAC component, so I hooked up a pulse voltage to B9 while grounding all other input signals. I also attached a capacitor to the output node, and I got the following results. The time delay was calculated by
Next, I needed to calculate the output of various loads being driven by a modified version of the ideal ADC to DAC converter (using our own component instead of an ideal DAC).
No Load
Since there was no load at the output node, the measured value was taken from the input values.
Under 10pF Capacitor Load
The capacitor adds a lag on the output voltage since it takes time to charge and discharge. This lag time delays the output voltage from the input voltage.
Under 10k Resistive Load
The input signal to the DAC is the ADC component, which outputs 9 bits that are used in the conversion. The steps are explained from the input signal building the amplitude of the voltage. The resistor at the output node creates a larger voltage drop, decreasing the amplitude of the output wave.
The output is delayed from the capacitor delay time to charge and discharge, the amplitude is affected by the resistor since there is a larger voltage drop on the output node less output voltage is measured.
Let's say that the switches in the Figure 30.14 had a much larger resistance than R in the schematic, the larger resistance overall would affect the circuit by drawing more current through the load, creating a greater voltage drop, therefore limiting the amount of voltage seen in the output. Specifially, the large value (transistor resistance) value would have to be known in order to calculate the magnitude of how the output voltage is decreased by.
The last step in the lab, is documenting how all the important lab information is being backed up. To do this, I create a zip that contains the following: all important pictures included in this lab report. The lab report itself, and any other miscellaneous important information from the lab, I then save everything into my google docs page where I have a separate folder for EE421L.
This concludes the Lab 2 Report.