EE 421L - Project
Part 1
For the schematic I followed the designed depicted by Fig 18.23. I decided to design the schematic with two inverters. To make up for the inverted output signal, I switched the input signals D and Di to compensate.
Simulations
To set up the simulation, I set the input signals to 2.75V and 3V. The following settings for the ADE are set:
To set up the power simulation I set the direct plot to total power, and to calcualte the power I integrated the total power to get the wattage used per hour. I integrated the signal from 0 to 3600s.
To set up the DC simulation, I set one of the input signals to 2.5V and ran the DC simulation on the other input signal.
I increased the width of the two inverters at the end of the schematic of (4x) then (2x) respectively:
I then added a third inverter, and switched the inputs to simulate adding more hardware to the schematic.
I then increased the width difference to (2x):
Then I changed the period length of the input signals first to 4 ns then 10 ns. I also varied the input amplitudes to add more variety to the simulation results.
The Layout passes DRC and LVS.
NOTE: If there is a need to verify the DRC and LVS you will have to change the Rules Library to "NCSU_TechLib_ami06"