Lab 7

Lab 7 - ECE 421L

Authored by Do Le (led2@unlv.nevada.edu)

21st of October, 2020

Lab Description

The purpose of this lab is to work with buses and arrays of components.

During the lab schematics were created for the inverter, NAND gate, NOR gate, AND gate,

and OR gate. 8-bit word versions of the gates were created by using buses.

Mux/Demux were also created along with their 8-bit word versions.

Using full adders, an 8-bit adder was designed and laid out.

Prelab

Ring-Oscillator
    During the pre-lab, a ring-oscillator—a circuit that generates constant pulses was made.
    The ring oscillator was made using 31 inverters connected in series with a feedback loop.
    Here is the resulting schematic.
Oscillator0 Schematic

Simulation of the circuit yields the following waveform.
Oscillator0 Waveform

The schematic view for the oscillator is not compact enough, but can be replicated exactly using the following schematic.
Oscillator1 Schematic

A symbol was made for the ring oscillator.
Oscillator1 Symbol

The oscillator can be laid out by using inverter layouts created in previous labs. To verify that the circuit matches the intended schematic, an LVS was performed.
Oscillator1 Layout

A simulation of the resulting cell shows that the two schematic views are equivalent.
Oscillator1 Simulation

Lab

4x Inverter:

During the first part of the lab, a 4 bit word bus inverter is designed. This is simply created by connecting

four inverters together, however, this can be done easily by using buses and arrays as shown in the schematic below.

Inverter4 Schematic

To show that this functions identically to placing down four inverter, a transient simulation is produced using the resulting symbol.

Inverter4 Simulation Schematic

Here are the results:

Inverter4 Simulation Waveform

Bus NAND, NOR, AND, NOT, OR:

Using these same concepts, we can create 8-bit wide bus gates for the NAND, NOR, AND, NOT, and OR gate.

(Of course, these shortcuts do not apply to layout view).

The standard transistor level design of the one-bit input NAND, NOR, and NOT gates are shown.

The table below show the schematic design of each gate and their corresponding symbol.

Nand Transistor Level

Nor Transistor Level
Nor Schematic

Gates Symbols Schematic

NAND
NOR
NOT
AND
OR

We can perform a simulation of the gates to verify their operation using the following schematic.
AllGates8 Simulation Schematic

A transient simulation of the above yields predictable results (notice the various delays due to the load capacitance).
AllGates8 Simulation Waveform

MUX/DEMUX:
    MUX and DEMUX gates are gates that allow the signal path to be selected. In the MUX configuration, the select lines
    determine which input signal is taken to the output. In the DEMUX configuration, the select lines choose which outputs
    the input connects to. Here is a schematic of a 2 to 1 MUX/DEMUX, along with it's symbol.
MuxDemux Schematic

Using this schematic view, the operation of the circuit can be verified.
MuxDemux Simulation Schematic

Here are the results of the transient simulation.
MuxDemux Simulation Waveform

Now we can create 8-bit wide word MUX/DEMUX using the concepts introduced earlier. To keep signals compact an inverter is used
for Si within the cell. Here is the schematic followed by the new symbol.
MuxDemux8 Schematic

A final verification of the 8-bit word MUX/DEMUX is performed by modifying the original schematic
used for simulation.
MuxDemux8 Simulation Schematic

Here are the results.
MuxDemux Simulation Waveform

Full Adder:
    The final design is of an 8-bit full adder. To start, we design a single full adder that adds
    inputs A, B, and Cin and generates a sum result S, and carrout result Cout. This time the whole
    full adder is implemented in the transistor level and looks like this.
FullAdder Schematic