Lab

Lab 2 - EE421L

Authored by Rhyan Granados

9/2/20

Goal

To implement n-well resistors in a 10-bit DAC. The design will be based on this schematic below which is taken from Dr. Baker's CMOS fourth edition book.

Prelab

We are to download the lab2.zip to our desktop, upload and unzip it to our CMOSedu directory.

Then we open Cadence, click on the lab2 library that we uploaded, and select ideal_ADC_DAC schematic. From there we launch the ADE L and load the preset spectre state to get our Vout(blue) and Vin(red).

The difference between between ADC and the DAC is in their name: the ADC converts from analog to digital, and the DAC converts from digital to analog.

The relationship between Vin, B[9:0], and Vout is: Vin is taken by the ADC and converted to binary where it is assigned to the B pins. From there, the ADC takes the binary numbers and converts them to a waveform which is Vout.

To calculate the LSB(least significant bit) we take the reference voltage VDD divide by 2 to the N( the number of bits).

The Lab

To start off I created a symbol for my voltage divider that I will stack 10 times for each of the 10 bits in the 10 bit DAC. I will open up a copy of the Ideal 10-bit DAC's schematic and stack the voltage divider symbol that I created to make the 10-bit DAC.

After making the 10-bit DAC with my voltage divider symbol, I will then make a symbol for my 10 bit DAC which I will be using in the main schematic.

I will open up a copy of the Ideal 10-bit DAC's schematic and stack the voltage divider symbol that I created to make the 10-bit DAC.

After making the 10-bit DAC with my voltage divider symbol, I will then make a symbol for my 10 bit DAC which I will be using in the main schematic.

Finally, I will open up a copy of the ideal_ADC_DAC schematic schematic that we used in the beginning and replace the DAC with my very own and sim it.

Below is the schematic with my own 10 bit DAC circled in yellow and the transient response to its left; it is identical to the original simulation in the beginning proving it operates properly.

2) To determine the output resistance of the DAC by combing resistors in parallel and series:

Bonus: How to find Vout of a DAC

3) Delay, driving a load

Below is a calculation of the time delay using td=0.7RC

From the transient response, we can see that at 70ns our Vout is 1.16; it is not 1.25 which would be half of 2.5 V which is our Vout max but it is close enough.

4) Simulations with driving a resistor, capacitor and both

Driving a 1 pF capacitor: We have a time delay in our Vout due to the capacitor.

Driving a 10k resistor: When we include a 10k resistor load we get half of our Vin which is 2.5V, and Vin and Vout are in phase. This further proves that the DAC has an equivalent resistance of 10k, because it also halved our input in our earlier simulation.

Driving a 10pF Capacitor and a 10k resistor: When we include a 10k resistor load and a capacitor after, there is still that 2.5V Vout and they are still in phase.

However, the capacitor smooths out the Vout signal.

5) In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).

In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs), when the resistance of the switches isn't small compared to R then tbe equivalent resistance would not be R. It would have to recalculated to match the load resistance and ensure maximum output.

6) Forcing the simulation to converge

Due to too low or too high impedances, converges may occur; I have tried to force it and I've noticed improvements in the waveform.

File Backup Proof

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