Lab 6 - ECE 421L
Lab:
Part 1: Drafting and Laying Out the NAND gate
For the first part of the lab we will first be drafting the schematic of the NAND gate. The NAND gate will be a 2 input gate and the schematic will include the use of 4 terminal transistors. For this lab we will be using the mosfet sizes of 6u/0.6u for both the NMOS and PMOS mosfet.
Figure 1 - NAND Gate Schematic
After checking the schematic for errors we will now create a symbol from the schematic.
Figure 2 - NAND Gate Symbol
Now the next step is to layout the NAND gate using the mosfet sizing we used for the schematic.
Figure 3 - NAND Gate Layout
After the NAND gate has been laid out we need to DRC the schematic, extract and then LVS the extracted and schematic files to check if the net lists match.
Figure 4 - NAND Gate DRC
Figure 5 - NAND Gate Extracted
Figure 6 - NAND Gate LVS
Part 2: Drafting and Laying Out the XOR Gate
For the next part of the lab we will first be drafting the schematic of the XOR gate, again using the mosfet sizing of 6u/0.6u for both the PMOS and NMOS. The XOR gate will also be a 2 input XOR gate.
Figure 7 - XOR Gate Schematic
After drafting the XOR gate we will check the schematic and then create the symbol for the schematic.
Figure 8 - XOR Gate Symbol
After the schematic and symbol are done its now time to layout the schematic for the XOR Gate. We will use Metal 1 to connect the pins into the circuit and use other material such as poly as well to connect gates of the mosfet together.
Figure 9 - XOR Gate Layout
After laying out the XOR gate we DRC, Extract and LVS the layout.
Figure 10 - XOR Gate DRC
Figure 11 - XOR Gate Extracted
Figure 12 - XOR Gate LVS
Part 3: Testing the Gates
The next part of the lab is to test the gates that we created. We will create a new schematic that implements all of the gates and then read the inputs and outputs of the gates.
Figure 13 - Gate Test Schematic
After Drafting the Schematic of the gates we will test using inputs in different period and compare the output results. The output results should match the outputs of standard XOR, NAND and Inverting gates.
Figure 14 - Gate Output Graph
Using the tables of all the gates we can compare the inputs and outputs and see that the gates are working correctly.
INVERTER
| A | A' |
| 0 | 1 |
| 1 | 0 |
NAND GATE
| A | B | A NAND B |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR GATE
| A | B | A XOR B |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
We can also see in the graph some sudden spikes going up or down. On the graph these spikes occure at the rising or falling edges of the input and output. This glitches occur as the inputs and outputs briefly rise and fall and during that period of rising and falling the gates output those suddent spikes. These spikes could be fixed using a faster rising time and falling time which should reduce the intensity of the spikes. In this schematic the rising time for the input pulse was 1ns.
Part 3: Drafting and Laying Out Full Adder
The next part of the lab is to draft the schematic of a full adder using the gates we designed and tested.
Figure 15 - Full Adder Schematic
After creating the schematic we will create a symbol for it as well.
Figure 16 - Full Adder Symbol
The next step is to layout the full adder, we can instantiate the layouts of the gates and then connect the inputs and outputs accordingly. For this layout, there will be 3 NAND gates and 2 XOR gates that will be instantiated onto the layout following the schematic.
Figure 17 - Full Adder Layout
After the layout is created we DRC, Extract and LVS. It is important to double check the connections for a bigger layout like this. Constant DRC throughout the process was done in order to fix the errors before they all piled up.
Figure 18 - Full Adder DRC
Figure 19 - Full Adder Extracted
Figure 20 - Full Adder LVS
Part 4: Implementing and Testing Full Adder
The final part of the lab is to implement the Full Adder and test it. We will create a schematic and test the inputs and outputs comparing it to the table of a full adder.
Figure 21 - Full Adder Test Schematic
After the full adder us implement we will use pulse inputs with varying periods on each of the inputs in order to get different inputs in the graph. We will then compare the inputs and outputs to the full adder table.
Figure 22 - Full Adder Graph
FULL ADDER
| a | b | cin | s | cout |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Using the table we can see that the graph of the full adder is correct.