Lab 5 - ECE 421L
For the prelab we will be going through Cadence Tutorial 3 which covers how to draft a schematic and layout of an inverter. Also note that it is important to backup all lab work.
Lab:
For the first part of this lab we will be using a PMOS with a width of 12u and an NMOS with a width of 6u both with sizes of 0.6u for the length. Using these mosfets we will first draft a schematic.
Figure 1 - Schematic for 12u/6u Inverter
After drafting the schematic we will now create the symbol from the Schematic for the Inverter.
Figure 2 - Symbol for 12u/6u Inverter
Now that the symbol is created it is now time to layout the Inverter. To layout the inverter we instantiate an PMOS and NMOS mosfet with their respective Ntap and Ptap for their bodies. We then connect the two gates together (Input A). PMOS source is connected to VDD! along with the Ntap body and the drain connected to the NMOS. NMOS drain is tied with PMOS drain, while the source goes to GND! along with the Ptap body.
Figure 3 - Layout for 12u/6u Inverter
After the layout is created, we need to DRC to check for errors and then Extract. After extracting we can do an LVS with the schematic to make sure there is a match.
Figure 4 - DRC of 12u/6u Inverter
Figure 5 - LVS of 12u/6u Inverter
Part 2: Drafting Schematics, Layouts and Symbols for Inverter 48u/24u
For the second part of the lab we will be using a PMOS with a width of 48u and an NMOS with a width of 24u. These sizes can be achieved by using an m=4 making it wider by 4 times. We will start by creating the schematic which will be the same but each mosfet with an m=4.
Figure 6 - Schematic of 48u/24u Inverter
After creating the schematic we will create the symbol.
Figure 7 - Symbol of 48u/24u Inverter
After the symbol is created it is now time to create the layout for the Inverter. To create the layout we must instantiate a PMOS and NMOS, this time we make sure to add m=4 or fingers=4. We will connect both of the gates together and then connect the drains together. The PMOS soruce goes to VDD! with body and the NMOS goes to GND! with body.
Figure 8 - Layout of 48u/24u Inverter
After creating the layout we will DRC to check for any errors and then finally extract. Once extracted we perform the LVS with our schematic.
Figure 9 - DRC of 48u/24u Inverter
Figure 10 - LVS of 48u/24u Inverter
Part 3: Simulating the Operation of the 12u/6u Inverter
For Part 3 we will be simulating our Inverter. We first need to create a schematic which we will be using to test the inverter and graph the input and output. We will be using this schematic for 4 different capacitive loads: a 100 fF, 1 pF, 10 pF, and 100 pF. After creating the schematic we will graph, using spectre, the input and output for each respective load for this 12u/6u inverter.
Figure 11 - 12u/6u Inverter Schematic for 100fF Load
Figure 12 - 12u/6u Inverter Graph for 100fF Load
Figure 13 - 12u/6u Inverter Schmatic for 1pF Load
Figure 14 - 12u/6u Inverter Graph for a 1pF Load
Figure 15 - 12u/6u Inverter Schematic for 10pF Load
Figure 16 - 12u/6u Inverter Graph for 10pF Load
Figure 17 - 12u/6u Inverter Schematic for 100pF Load
Figure 18 - 12u/6u Inverter Graph for 100pF Load
After creating the schematic and graphing all the different loads for this 12u/6u Inverter we will now graph them all again but this time using UltraSim. We can switch to UltraSim from spectre by going down the dropdown menu and selecting UltraSim. Note it is importent to set the MODEL LIBRARIES to your ami06 PMOS and NMOS files to avoid failure of loading the graphs.
Figure 19 - Switching to UltraSim
After switching we will now do the sweep on the capacitor from 100f to 100p instead of doing it all individually.
Figure 20 - Using UltraSim to Graph all Inverter CLoads
Part 4: Simulating the Operation of the 48u/24u Inverter
Now the next part of the lab is to repeat what was done for the 12u/6u Inverter and graph the input and output of a 48u/24u Inverter under different loads. We will first use spectre to graph the loads at: 100 fF, 1 pF, 10 pF, and 100 pF.
Figure 21 - 48u/24u Inverter Schematic with 100fF Load
Figure 22 - 48u/24u Inverter Graph with a 100fF Load
Figure 23 - 48u/24u Inverter Schematic with a 1pF Load
Figure 24 - 48u/24u Inverter Graph with a 1pF Load
Figure 25 - 48u/24u Inverter Schematic with a 10pF Load
Figure 26 - 48u/24u Inverter Graph with a 10pF Load
Figure 27 - 48u/24u Inverter Schematic with a 100pF Load
Figure 28 - 48u/24u Inverter with a 100pF Load
After grpahing all the inputs and outputs of different loads with spectre its now time to switch to UltraSim again. We will sweep the CLoad again to save time. Again, it's important to remember to have your model library setup so that the graph will work.
