Lab 3 - ECE 421L
For the prelab we will be backing up all of our files from the previous labs and reviewing tutorial 1 on Cadence specifically for creating n-well resistor layouts.
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Lab:
Width and Length can also be selected based on information on certain processes. In class we are using the C5 process, which based on ON Semiconductor the sheet resistance would be 855 ohms/square for the n-well.
Part 2: Designing the Layout of the DAC
After creating the n-well resistor, its time to create the DAC based on the information we gained though lab2. Using the same technique from lab2 I created the R Chain but this time using the n-wells. We first start by creating a layout and then instantiating the n-well we are using to create a layout in which there are two 10K n-well resistors in series then in parallel with one 10K. While creating the layout we have to keep in mind that the resistors should be laid out in parallel with the same x positions and varying y posistions. Another thing to keep in mind is that the resistors need to be spaced a certain way and in my case I used the ruler tool under the tools tab to measure the space between the reistors which should be 7.8um.
After creating the layout of the R Chain its important to check the layout by doing a DRC verification. Now that the R Chain is finished the next part is to work on putting the R Chains together and start on the DAC layout. We need a total of 10 R chains. To make it easy on creating the laying and making sure spacing is good, we need to instantiate one R Chain layout onto ourDAC layout and then we can copy it, press F3, and then make 10 rows of copies. The DAC layout should look something like this.
Not that there's an extra resistor at the bottom to account for the last 10K in the schematic. Now that the DAC layout is ready the next step is to create pins in the schematic and then connect the R Chains using metal1 in such a way where it mimicks the schematic from lab2. It is important to put down the pins B0 to B9, Vin, Vout and gnd.
Here's the beginning the of DAC, we can see the B9, Vout and B8 pins as well as how metal1 will be connected throughout the rest of the chains.
Here is the ending of the DAC where we can see the LSB bit as well as the extra single n-well resistor added at the end. When the DAC layout is finished all that's left is to do a DRC check, extract the layout, and finally do an LVS with the extracted layout and original DAC schematic from lab2.
