Lab X - ECE 421L 

Authored by Tian Chen

9/8/2020

chent5@unlv.nevada.edu

Prelab:

We load the lab2 demo file into virtuoso and run the simulation of it here is the schmatic.

And we load the state of the simulation and we got this graph.

Lab 2:

We will need to build our own DAC the first step is to build the induvial DAC bit and here is the schematic.

And we make the symbol out of this and we got this.

After this step we will use the single bit to make a 10 bit DAC, and here is the schematic.


We will need to make a symbol out of this DAC.



After that we can put the DAC we build into the schematic and test the performace of it.

Here is the simulation result of the DAC that we build.

And now we are going to test the delay response when we add a cap on the output

We got it the 1/2t = 0.7RC

Then we are putting a resistor in the end to see if it will pull the signal down





Then we are putting a cap between the Vout and the cap to see if that will smooth out the signal.



And i back this up at my google drive





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