Lab 3 - ECE 421L
In the previous lab we build the schematic for the DAC voltage divder and also the 10_bit DAC. Now in this lab we are going to build the layout of the resistors. From that step we are going to make the 10_bit DAC layout.
The first step is to make the resistor layout on thr n-well layer. Here is the layout.
Here is the extracted form of the N-well resistor.
The second step is to make the DAC single bit layout out of the resisotor that we create. Extracted that and then perform DRC and LVS with the schematic that we create last week.
The third step is to make the layout of the 10bit_DAC out of the single bit DAC that we got to perform DRC and LVS.
When we pass the LVS we can run the simulation though the ADE in cadence. Here is the simulation result that we got.
Postlab :
I backed all the work in my google cloud drive.