"Design, layout, and simulate a digital receiver circuit that accepts a high-speed digital input signal D and Di (a differential pair
connected to your circuit from, for example, a twisted pair of wires such as in an Ethernet cable). D and Di are complements so,
for example, if D is 5V then Di is 0V and output = 1. Another example, where D is 1V and Di is 2V, then output = 0. At high speeds
and long distances, the voltages received aren't full digital logic levels (i.e., 5V and 0V), hence the need to design, and use, a
high-speed digital recevier circuit. Ideally, when D > Di the receiver outputs a 1. When D < Di the receiver outputs a 0. Base your
design on the topology seen in Fig. 18.23. Try to design for high-speed and low-power. Characterize your design (in sims) and
the trade-offs. For example, show that you get higher-speed if you use more energy (burn more power). See if you can get, in this
500 nm process, 250 Mbits/s (a bit width of 4 ns) with an input voltage difference of, for example, 250 mV (with D and Di swinging
back and forth between 2.75V and 3V, for one of many examples, your circuit outputs the correspondingly correct values). Note that
while Fig. 18.23 shows one inverter on the output you may find, for example, that two inverters work better (at the cost of power). Use
a table to summarize your design's performance."
As the difference in between the two inputs increases, the output waveform gets significantly sharper, the delay time decreases, and the average power consumption decreases. Also, this original circuit does not work very well near the Vcc.
To start improving this circuit, I will add an inverter to the schematic and run the same simulations again. Then, I'll make a table to compare the two circuits, as per the requirements specified in the project objective section.
New Schematic:
I used the same simulator circuit as last time.
Objective Specified Conditions:
0 and 4 volts at 250 Mhz:
0 and 5 volts (ideal) at 250 Mhz:
The waveforms clearly show that the rise and fall times of the new circuit are a significant improvement over the original. This comes at the expense of a very slight increase in average power consumption. Unfortunately, the high voltage performance is significantly worse.
Original Circuit Power (mW) | Added Inverter Power (mW) | Waveform Acuity (original) | Waveform Acuity (added Inverter) | |
| Objective Specified Conditions: | 8.66 | 9.04 | Poor | Good |
| 4.25 and 4.5 volts at 250MHz: | 8.00 | 5.54 | Very Poor | Very Poor |
| 2.5 and 2.25 volts at 250MHz: | 8.77 | 9.16 | Poor | Good |
| 1.5 and 1.75 volts and 250 MHz: | 8.66 | 9.06 | Moderate | Good |
| 0 and 2 volts at 250 MHz: | 6.31 | 6.56 | Good | Good |
| 0 and 4 volts at 250 Mhz: | 5.19 | 5.43 | Good | Excellent |
| 0 and 5 volts (ideal) at 250 Mhz: | 5.11 | 5.17 | Good | Excellent |
It is self evident from the table that adding a second inverter improves the circuit's performance. It is difficult to make further improvements to the circuit without significant trade-offs. This is the direct result of one simple equation:
In order to further characterize the design, I included a number of additional simulations. First, I will show what the minimum input voltage difference is where the circuit is still effective. I will then show what the circuit's minimum VDD is, and finally I will show the effect of temperature on the circuit. I will be using the same simulation circuit schematic shown in the first group of images, with modified parameters of course.
To determine the minimum input difference, I started by splitting the 250mV difference in half to 125mV. I decided that I would vary between 2.5 and 2.625 volts, since the circuit seems to work best in the middle of its range. As you can see, at 250 MHz, the circuit still works fairly well:
I decided to push a little lower to 100mV, which was still very effective:
I then tried a difference of 50mV, where the circuit was still very effective:
Finally, I tried to use a 10mV difference. 10mV is too low for proper function, but the circuit still does try to output:
Next up was to test different VDDs. I used the conditions specified in the objective for this test, which is a 250mV difference at a frequency of 250MHz.
4 Volts:
3.5 Volts:
3 Volts:
3.7 Volts:
So the lowest VDD that can be withstood by the circuit is 3.8 volts. When the VDD is decreased, the max output voltage decreases to the level of VDD.
Next, I ran some temperature simulations. I ran 4 temperature simulations at the objective specified conditions. In order, the temperatures I ran are -30 C, 0 C, 100C, and 150C. The results were as follows:
As you can see, the operating temperature of the circuit is not a huge determining factor in the circuit performance. Cold has nearly no influence on the performance, but heat causes noticeable degradation.
In this final portion of the lab, I will be laying out my design in Cadence and running an LVS. The layout was not too difficult. It is shown below:
Here is the proof of DRC and LVS.
This concludes the final project.