Lab 5 - EE 421L Fall 2020

Authored by Xianjie Cao

21 September, 2020

Pre-lab work:

For our Pre-lab work, we should go through the tutorial 3, which it explains how to draw the schmatic, symbol and layout of a CMOS inverter.

The schematic of the inverter is as following, it was using a 12u/0.6u PMOS and a 6u/0.6u NMOS.

The symbol of the inverter:

The layout view and the extracted view of the inverter:

it passes the DRC and the LVS verification.

We will then start simulating the inverter, Here is the schematic of the circuit. Make sure we include vdd, but do not connect vdd to the input voltage source.

Also, remember to enable the Global Sources in the ADE, select Setup -> Stimuli.

The output is as following:

Lab description:

Make two inverters having sizes of 12u/6u and 48u/24u, draft schematics, layouts and symbols for both. Then using SPICE and UltraSim to simulate both inverters driving a 100 fF, 1pF, 10pF and 100pF capacitive load.

Lab procedures:

1) Schematic and symbol for 12u/6u inverter.

2) Layout of the 12u/6u inverter, and the proof of passing DRC and LVS. 

3) Schematic and symbol for 48u/24u inverter.

The above schematic has m = 4, that is, mutiplier, implies that the size is 4 * 12u and 4*6u

4) Layout of the 48u/24u inverter with proof of passing DRC and LVS.

5) Simulations(100fF to 100pF capacitive load) with 12u/6u inverter.

Instead of running four simulations with different values of capacitance, we can use parametric analysis with capacitor as variable. 

Schematic:

Spectre Simulation:

UltraSim:

6) Simulations (100fF to 100pF capacitive load) with 48u/24u inverter.

Schematic:

Spectre Simulation:

UltraSim:

From our simulations, we can see that the four finger inverter has better output, because it has more MOSFET that allow the capacitor to charge and discharge efficiently.

For back-ups:
zipped the library folder and the folder that has all the collected images to the desktop, then upload them into my personal github repository for backups.

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